• The Journal of the Institute of Internet, Broadcasting and Communication
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• v.12 no.6
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• pp.257-264
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• 2012

In this paper, we propose a Route Stability-based Direction Guided Routing protocol(RSDGR) in mobile ad-hoc wireless networks. The main features and contributions of the proposed routing protocol are as follows. First, it can calculate link stability between two nodes as well as route stability of multi hop quantitatively by using nodes' mobility. And this protocol can establish the most stable path between a source node and a destination node. Second, according to the route stability between a source node and a destination node, it can control and optimize the direction guided region dynamically for route setup. Third, we suggest theoretical model for quantitative calculation of link stability between two nodes and route stability of multi hop path. The performance evaluation of the proposed routing protocol is performed by simulation using OPNET(Optimized Network Engineering Tool) and theoretical analysis. The results of performance evaluation show that the patterns of PDR are similar in simulation and analysis according to route stability. The faster mobile nodes' velocity and the smaller source node's direct guided reigion, the lower route stability and PDR and the higher delay and control overhead related to this.

• Journal of the Institute of Electronics Engineers of Korea TC
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• v.38 no.12
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• pp.1-9
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• 2001

In the APON(ATM Passive Optical Network), the transmission of the upstream traffic is based on a TDMA(Time Division Multiple Access) method that an OLT(Optical Line Termination) permits ONUs(Optical Network Units) sending cells by allocating time slots. Because the upstream is not a streaming mode, the cell synchronizer has to be operated in the burst mode. Also, the cell phase monitor is required to prevent collisions between cells which are transmitted by multiple ONUs through a single optical fiber. In this paper, a TDMA burst cell synchroniser is implemented with the FPGA(Field Programmable Gate Array) being used in the APON based on G.983.1 for transmitting upstream cells. It has two main functions which are the upstream data recovery and the phase monitoring. The former is to recover the upstream data and clock in the OLT by seeking the preamble which is the overhead of the upstream time slot and by aligning the phase of the bit and cell with the system clock. The latter is to provide the information to the ONU to compensate for the equalization delay by monitoring continuously the phase difference between adjacent cells to avoid the cell collision on the upstream.

• Journal of the Institute of Electronics Engineers of Korea SD
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• v.46 no.3
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• pp.26-31
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• 2009

A new LFSR based test compression scheme is proposed by reducing the maximum number of specified bits in the test cube set, smax, virtually. The performance of a conventional LFSR reseeding scheme highly depends on smax. In this paper, by using different clock frequencies between an LFSR and scan chains, and grouping the scan cells, we could reduce smax virtually. H the clock frequency which is slower than the clock frequency for the scan chain by n times is used for LFSR, successive n scan cells are filled with the same data; such that the number of specified bits can be reduced with an efficient grouping of scan cells. Since the efficiency of the proposed scheme depends on the grouping mechanism, a new graph-based scan cell grouping heuristic has been proposed. The simulation results on the largest ISCAS 89 benchmark circuit show that the proposed scheme requires less memory storage with significantly smaller area overhead compared to the previous test compression schemes.

• Journal of the Institute of Electronics Engineers of Korea SD
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• v.47 no.4
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• pp.50-61
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• 2010

Nowadays, the SoC is watched by all over the world with interest. The design trend of the SoC is hardware and software co-design which includes the design of hardware structure in RTL level and the development of embedded software. Also the technology is toward deep-submicron and the observability of the SoC's internal state is not easy. Because of the above reasons, the SoC debug is very difficult and time-consuming. So we need a reliable debugger to find the bugs in the SoC and embedded software. In this paper, we developed a hardware debugger named OCD. It is based on IEEE 1140.1 JTAG standard. In order to verify the operation of OCD, it is integrated into the 32bit RISC processor - Core-A (Core-A is the unique embedded processor designed by Korea) and is tested by interconnecting with software debugger. When embedding the OCD in Core-A, there is 14.7% gate count overhead. We can modify the DCU which occupies 2% gate count in OCD to adapt with other processors as a debugger.

• Journal of the Institute of Electronics Engineers of Korea TC
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• v.44 no.10
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• pp.119-126
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• 2007

Recently, the mobility of users and mobile communication technologies have developed rapidly. The users in this state also want to connect their devices and to receive services anywhere, anytime. Hierarchical Mobile IPv6 (HMIPv6) has been proposed by the Internet Engineering Task Force (IETF) to compensate for such problems as handover latency and signaling overhead when employing Mobile IPv6 (MIPv6). HMIPv6 supports micro-mobility within a domain and introduces a new entity, namely Mobility Anchor Point (MAP) as a local home agent. However, HMIPv6 has been found to cause longer handover latency when the inter-domain handover occurs. This is because a Mobile Node (MN) has to generate two addresses and register them to Home Agent (HA) a MAP, respectively. In order to solve such problems, we propose a scheme that an MN generates one address and registers it to HA for supporting fast handover during the inter-domain handover process. In the proposed scheme, the load of MAP and MAP domain is reduced because the number of MNs which are managed by MAP is decreased and the MAP does not perform proxy Neighbor Discovery Protocol (NDP) to intercept packets destined to MNs. We evaluate the performance of proposed scheme in comparison to HMIPv6 through the simulation and numerical analysis.

• Journal of the Korea Society of Computer and Information
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• v.17 no.5
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• pp.1-7
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• 2012

In this paper, we design and implement the simulator for WAN storage replication model performance evaluation in cloud computing environment. Each cloud of simulator is composed of virtual machine emulator and storage emulator. The virtual machine emulator is composed of read/write ratio module, the read/write sequence combination module, and the read/write request module. The storage emulator is composed of storage management module, data transfer module, read/write operations module, and overhead processing module. Using the simulator, we evaluate performance of migration scheme, pre-copy and the post-copy, considering about read/write ratio, network delay, and network bandwidth. Through simulation, we have confirmed that the average migration time of pre-copy was decreased proportional to the read operation. However, average migration time of post-copy was on the increase. Also, the average migration time of post-copy was increased proportional to the network delay. However, average migration time of pre-copy was shown uniformly. Therefore, we show that pre-copy model more effective to reduce the average migration time than the post-copy model. The average migration time of pre-copy and post-copy were not affected by the change of network bandwidth. Therefore, these results show that selects the storage replication model to be, the network bandwidth know not being the important element.

• Journal of the Korea Society of Computer and Information
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• v.16 no.10
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• pp.1-10
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• 2011

There are the large overhead of block erase and page write operations in NAND flash memory, though it has low power consumption, cheap prices and a large storage. Due to the physical characteristics of NAND flash memory, overwrite operations are not permitted at the same location, so rewriting operation require after erase operation. it cause performance decrease of NAND flash memory. Using SRAM buffer in traditional NAND flash memory, it can not only reduce effective write operation but also guarantee fast memory access time. In this paper, we proposed the small SRAM buffer management system for reducing overhead of NAND flash memory, that is, erase and write operations. The proposed buffer system in a NAND flash memory consists of two parts, i.e., a fully associative temporal buffer with the small fetching block size and a fully associative spatial buffer with the large fetching block size. The temporal buffer have small fetching blocks that referenced from spatial buffer. When it happen write operations or erase operations in NAND flash memory, the related fetching blocks in temporal buffer include a page or a block are written in NAND flash memory at the same time. The writing and erasing counts in NAND flash memory can be reduced. According to the simulation results, although we have high miss ratios, write and erase operations can be reduced approximatively 58% and 83% respectively. Also the average memory access times are improved about 84% compared with the fully associative buffer with two sizes.

• Journal of Korea Spatial Information System Society
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• v.8 no.2 s.17
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• pp.13-38
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• 2006

Range query is one of the most important operations for spatial objects, it retrieves all spatial objects that overlap a given query region in multi-dimensional space. The DOT(DOuble Transformation) is known as an efficient indexing methods, it transforms the MBR of a spatial object into a single numeric value using a space filling curve, and stores the value in a $B^+$-tree. The DOT index is possible to be employed as a primary index for spatial objects. However, the range query processing based on the DOT index requires much overhead for spatial transformations to get the query region in the final space. Also, the detailed range query processing method for 2-dimensional spatial objects has not been studied yet in this paper, we propose an efficient multi-dimensional range query processing technique based on the DOT index. The proposed technique exploits the regularities in the moving patterns of space filling curves to divide a query region into a set of maximal sub-legions within which space filling curves traverse without interruption. Such division reduces the number of spatial transformations required to perform the range query and thus improves the performance of range query processing. A visual simulator is developed to show the evaluation method and the performance of our technique.

• Tunnel and Underground Space
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• v.30 no.5
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• pp.496-507
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• 2020

A prediction of the performance of EPB TBM is significant for improving the constructability of tunnels. Thus, various attempts to simulate TBM excavation by the numerical method have been made until these days. In this paper, to evaluate the performance of TBM with different operating conditions, a parametric study was carried out using coupled discrete element method (DEM) and finite difference method (FDM) EPB TBM driving model. The analysis was conducted by changing the penetration rate (0.5 and 1.0 mm/sec) and the rotational speed of screw conveyor (5, 15, and 25 rpm) while the rotation velocity of the cutter head kept constant at 2 rpm. The torque, thrust force, chamber pressure, and discharging with different TBM operating conditions were compared. The result of parametric study shows that the optimum driving condition can be determined by the coupled DEM-FDM numerical model.

• Tunnel and Underground Space
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• v.30 no.5
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• pp.484-495
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• 2020

To numerically simulate the advance of EPB TBM, various type of numerical analysis methods have been adopted including discrete element method (DEM), finite element method (FEM), and finite difference method (FDM). In this paper, an EPB TBM driving model was proposed by using coupled DEM-FDM. In the numerical model, DEM was applied in the TBM excavation area, and contact properties of particles were calibrated by a series of triaxial tests. Since the ground around the excavation area was coupled with FDM, the horizontal stress considering the coefficient of earth pressure at rest could be applied. Also, the number of required particles was reduced and the efficiency of the analysis was increased. The proposed model can control the advance rate and rotational speed of the cutter head and screw conveyor, and derive the torque, thrust force, chamber pressure, and discharging during TBM tunnelling.