• Proceedings of the Korean Institute of Information and Commucation Sciences Conference
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• 2012.05a
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• pp.693-695
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• 2012

This paper have presented the breakdown voltage for double gate(DG) MOSFET. The analytical solution of Poisson's equation and Fulop's breakdown condition have been used to analyze for breakdown voltage. The double gate(DG) MOSFET as the device to be able to use until nano scale has the adventage to reduce the short channel effects. But we need the study for the breakdown voltage of DGMOSFET since the decrease of the breakdown voltage is unavoidable. To approximate with experimental values, we have used the Gaussian function as charge distribution for Poisson's equation, and the change of breakdown voltage has been observed for device geometry. Since this potential model has been verified in the previous papers, we have used this model to analyze the breakdown voltage. As a result to observe the breakdown voltage, the smaller channel length and the higher doping concentration become, the smaller the breakdown voltage becomes. Also we have observed the change od the breakdown voltage for gate oxide thickness and channel thickness.

• Journal of the Korea Institute of Information and Communication Engineering
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• v.17 no.2
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• pp.372-377
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• 2013

This paper have presented the breakdown voltage for double gate(DG) MOSFET. The analytical solution of Poisson's equation and Fulop's breakdown condition have been used to analyze for breakdown voltage. The double gate(DG) MOSFET has the advantage to reduce the short channel effects as improving the current controllability of gate. But we need the study for the breakdown voltage of DGMOSFET since the decrease of the breakdown voltage is unavoidable. To approximate with experimental values, we have used the Gaussian function as charge distribution for Poisson's equation, and the change of breakdown voltage has been observed for device geometry. Since this potential model has been verified in the previous papers, we have used this model to analyze the breakdown voltage. As a result to observe the breakdown voltage, the smaller channel length and the higher doping concentration become, the smaller the breakdown voltage becomes. Also we have observed the change of the breakdown voltage for gate oxide thickness and channel thickness.

• Journal of the Korea Institute of Information and Communication Engineering
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• v.17 no.4
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• pp.917-921
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• 2013

This paper have analyzed the change of breakdown voltage for conduction path of double gate(DG) MOSFET. The low breakdown voltage among the short channel effects of DGMOSFET have become obstacles of device operation. The analytical solution of Poisson's equation have been used to analyze the breakdown voltage, and Gaussian function been used as carrier distribution to analyze closely for experimental results. The change of breakdown voltages for conduction path have been analyzed for device parameters such as channel length, channel thickness, gate oxide thickness and doping concentration. Since this potential model has been verified in the previous papers, we have used this model to analyze the breakdown voltage. Resultly, we know the breakdown voltage is greatly influenced on the change of conduction path for device parameters of DGMOSFET.

• Proceedings of the KIEE Conference
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• 2009.07a
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• pp.1227_1228
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• 2009

본 논문에서는 순방향 특성의 열화 없이 항복전압 향상을 위해 플로팅게이트와 필드플레이트를 적용한 AlGaN/GaN HEMTs를 제작하였다. AlGaN/GaN HEMTs에서의 항복전압은 게이트의 하단의 전계분포와 관련이 있다. 제안된 AlGaN/GaN HEMTs의 경우 GaN 층의 공핍영역을 효과적으로 확장시킴으로써 게이트와 드레인 사이의 영역에서의 전계집중을 성공적으로 완화시켰다. 필드플레이트와 플로팅게이트가 모두 적용된 소자의 항복전압이 1106 V인 반면, 필드플레이트만 적용한 소자의 항복전압은 688 V, 플로팅게이트만 적용한 소자의 항복전압은 828 V로 측정되었다.

• Proceedings of the KIEE Conference
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• 2008.10a
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• pp.127-128
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• 2008

Baliga는 구형 PN 접합에 대한 해석적인 항복전압을 유도하였으며, 이 식은 ${\gamma}(r_j/W_{pp})$ 값이 1보다 큰 구간에서 구형 접합의 항복전압이 원통형 및 평면형 항복진압 보다 큰 값을 가지게 된다. 기본적으로 구형 접합의 한복전압이 원통형과 평면형 접합의 항복전압보다 클 수 없기 때문에 이는 명백한 오류이다. 이 오류는 식을 구하는 과정에서 소수점 두 자리를 무시하고 계산을 하였기 때문임을 밝혀냈으며, 또한 이러한 작은 실수가 구형 접합의 항복전압에 미치는 영향이 지대할 수 있다는 결과를 보고하고자 한다.

• Proceedings of the IEEK Conference
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• 1998.10a
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• pp.649-652
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• 1998

본 논문에서는 MICROTEC〔3,4〕시뮬레이터를 이용하여 소트키 다이오드를 형성하고 금속-반도체 쇼트키 접촉에서 턴 온 전압과 항복 전압을 관찰하였다. 또한 여러 가지 쇼트키 장벽 높이를 가지는 금속을 사용하여 동일한 디바이스에서 이들 금속-반도체 접촉에 전압을 인가했을 때, 순 방향에서 턴 온 특성을 관찰하여 턴 온 전압과 역 방향에서의 항복 현상을 관찰하여 항복 전압을 확인하였다. 사용된 금속은 Au(0.8V), Mo(0.68V), Pt(0.9V), Ti(0.5V) 이며 반도체는 실리콘 n/n 구조가 형성되었다. 쇼트키 다이오드는 대 전력용 보다는 높은 속도의 스위칭 디바이스에 주로 응용되고 있으며 장벽의 높이가 높을수록 뚜렷한 정류 특성을 나타내어 순 방향 바이어스에서 빠른 턴 온 특성이 예상되는데 시뮬레이션 결과 또한 잘 일치하였다. 그리고 다이오드의 I-V 특성을 관찰하기 위해 역 방향 바이어스에서의 항복 전압을 관찰하였는데 쇼트키 장벽이 높을수록 낮은 항복 전압이 나타났다. 또한 디바이스 공정에서 epitaxial과 열처리 공정 후의 2차원적인 농도 분포를 나타내었다.

• Proceedings of the KIEE Conference
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• 2005.11a
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• pp.57-59
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• 2005

전력용 IC에서 높은 항복전압의 구현을 위해서 RESURF구조가 많이 사용되고 있다. 하지만 하나의 칩 위에서 다양한 항복전압을 가지는 소자를 구현하기 위해서는 에피층의 농도가 각각 달라져야하는데 이는 공정상의 복잡함과 비용의 문제를 수반하게 된다. 이런 문제점에 따라 본 연구에서는 전력용 IC에서 항복전압이 다른 다수의 LDMOST를 추가 공정없이 에피 영역의 길이를 조절하여 구현할 수 있음을 해석적인 방볍과 2차원 소자 시뮬레이터를 이용하여 확인하였다.

• Journal of the Korea Institute of Information and Communication Engineering
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• v.21 no.6
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• pp.1069-1074
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• 2017

Reduction of breakdown voltage is serious short channel effect (SCE) by shrink of channel length. The deviation of breakdown voltage for doping concentration is investigated with structural parameters of sub-10 nm double gate (DG) MOSFET in this paper. To analyze this, thermionic and tunneling current are derived from analytical potential distribution, and breakdown voltage is defined as drain voltage when the sum of two currents is $10{\mu}A$. As a result, breakdown voltage increases with increase of doping concentration. Breakdown voltage decreases by reduction of channel length. In order to solve this problem, it is found that silicon and oxide thicknesses should be kept very small. In particular, as contributions of tunneling current increases, breakdown voltage increases.

• Journal of the Korea Institute of Information and Communication Engineering
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• v.20 no.9
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• pp.1771-1777
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• 2016

In this thesis, the breakdown voltage characteristics of silicon nanowire N-channel GAA MOSFETs were analyzed through experiments and 3-dimensional device simulation. GAA MOSFETs with the gate length of 250nm, the gate dielectrics thickness of 6nm and the channel width ranged from 400nm to 3.2um were used. The breakdown voltage was decreased with increasing gate voltage but it was increased at high gate voltage. The decrease of breakdown voltage with increasing channel width is believed due to the increased current gain of parasitic transistor, which was resulted from the increased potential in channel center through floating body effects. When the positive charge was trapped into the gate dielectrics after gate stress, the breakdown voltage was decreased due to the increased potential in channel center. When the negative charge was trapped into the gate dielectrics after gate stress, the breakdown voltage was increased due to the decreased potential in channel center. We confirmed that the measurement results were agreed with the device simulation results.

• Proceedings of the Korean Institute of Information and Commucation Sciences Conference
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• 2017.05a
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• pp.688-690
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• 2017

Reduction of breakdown voltage is serious short channel effect (SCE) by shrink of channel length. The SCE occurred in on-state transistor raises limitation of operation range of transistor. The deviation of breakdown voltage for doping concentration is investigated with structural parameters of sub-10 nm double gate (DG) MOSFET in this paper. To analyze this, thermionic and tunneling current are derived from analytical potential distribution, and breakdown voltage is defined as drain voltage when the sum of two currents is $10{\mu}A$. As a result, breakdown voltage increases with increase of doping concentration. Breakdown voltage decreases by reduction of channel length. In order to solve this problem, it is found that silicon and oxide thicknesses should be kept very small. In particular, as contributions of tunneling current increases, breakdown voltage increases.