• The KIPS Transactions:PartC
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• v.8C no.1
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• pp.32-40
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• 2001

In this paper, we propose a high-speed modular multiplication algorithm which revises conventional Montgomery's algorithm. A hardware architecture is also presented to implement 1024-bit RSA cryptosystem for digital signature based on the proposed algorithm. Each iteration in our approach requires only one addition operation for two n-bit integers, while that in Montgomery's requires two addition operations for three n-bit integers. The system which is modelled in VHDL(VHSIC Hardware Description Language) is simulated in functionally through the use of $Synopsys^{TM}$ tools on a Axil-320 workstation, where Altera 10K libraries are used for logic synthesis. For FPGA implementation, timing simulation is also performed through the use of Altera MAX + PLUS II. Experimental results show that the proposed RSA cryptosystem has distinctive features that not only computation speed is faster but also hardware area is drastically reduced compared to conventional approach.

• Journal of the Korea Institute of Information and Communication Engineering
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• v.15 no.9
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• pp.1993-1999
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• 2011

This paper describes a design of area-efficient/low-power cryptographic processor for HIGHT block cipher algorithm, which was approved as standard of cryptographic algorithm by KATS(Korean Agency for Technology and Standards) and ISO/IEC. The HIGHT algorithm, which is suitable for ubiquitous computing devices such as a sensor in USN or a RFID tag, encrypts a 64-bit data block with a 128-bit cipher key to make a 64-bit cipher text, and vice versa. For area-efficient and low-power implementation, we optimize round transform block and key scheduler to share hardware resources for encryption and decryption. The HIGHT64 core synthesized using a 0.35-${\mu}m$ CMOS cell library consists of 3,226 gates, and the estimated throughput is 150-Mbps with 80-MHz@2.5-V clock.

• Geophysics and Geophysical Exploration
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• v.6 no.1
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• pp.13-22
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• 2003

TSP (Tunnel Seismic Profiling) survey is a technique for imaging and characterizing geological structures ahead of a tunnel face. The seismic modeling algorithm and the synthetic data could be helpful for TSP surveys. However, there is few algorithm to describe the propagation of the elastic waves around the tunnel. In this study, existing 2-dimensional seismic modeling algorithm using finite element method was modified to make a suitable algorithm for TSP modeling. Using this algorithm, TSP modeling was practiced in some models. And the synthetic data was analyzed to examine the propagation characteristics of the elastic waves. First of all, the modeling for the homogeneous tunnel model was practiced to examine the propagation characteristics of the direct waves in the vicinity of the tunnel. And the algorithm was applied to some models having reflector which is perpendicular or parallel to the excavation direction. From these, the propagation characteristics of the reflected waves were examined. Furthermore, two source-receiver arrays were used in respective models to investigate the properties of the two arrays. These modeling algorithm and synthetic data could be helpful in interpreting TSP survey data, developing inversion algorithm and designing new source-receiver arrays.

• The Journal of the Korea institute of electronic communication sciences
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• v.9 no.4
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• pp.447-454
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• 2014

Recently most of functional synthesis methods for quantum circuit realization have a tendency to adopt the declarative functional expression more suitable for computer algorithms, so it's difficult to analysis synthesized quantum functions. This paper presents a new functional representation of quantum circuits compatible with simple architecture and intuitive thinking. The proposal of this paper is a new functional synthesis development by using the control functions as the power of corresponding to affine-controlled quantum gates based on the mathematical substitution of serial-product matrix operation over the target line for the arithmetic and modulo-2 ones between power functions of unitary operators. The functional synthesis algorithm proposed in this paper is useful for the functional expressions and synthesis using both of reversible and irreversible affine-controlled NCV-quantum gates.

• Proceedings of the IEEK Conference
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• 2001.09a
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• pp.253-256
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• 2001

G.UTE ADSL 모뎀에 적합한 주파수 영역 프로세서의 구조를 제안하였다. 주파수 영역의 연산과정에 대한 알고리듬 수준의 최적화를 수행하였고, 하드웨어 자원할당에 따른 설계의 효율성도 분석하였다. 제안된 프로세서는 한 개의 실수 곱셈기와 두 개의 실수 덧셈기를 병렬로 연결한 구조를 가지며, 기존의 연구결과에 비해 작은 하드웨어 크기를 차지한다. 설계된 시스템은 삼성 0.35㎛ 표준셀 라이브러리를 사용하여 합성하였으며, G.LITE ADSL 모뎀에 적합하게 적은 하드웨어 자원으로 필요한 연산을 효율적으로 수행한다.

• Proceedings of the IEEK Conference
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• 1998.10a
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• pp.1251-1254
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• 1998

본 논문에서는 최근들어 널리 연구되고 있는 다해상도 신호해석 방법인 웨이브렛 변환, 웨이브렛 패킷, 그리고 코사인 패킷 알고리듬을 음성개선에 이용하여 각각의 성능을 비교하였으며, 또한 이를 기존의 스펙트럼차감법의 성능과 비교 분석 하였다. 성능비교의 척도로는 SNR과 ㅋ스트랄 거리를 이용하였다. 실험결과 SNR면에서는 코사인 패킷이 가장 좋은 결과를 보였다. 그리고 ㅋ스트랄 거리의 경우 코사인 패킷과 웨이브렛 패켓이 훨씬 나은 결과를 보였으며 주관적인 청취결과 역시 코사인 패킷이 가장 좋은 결과를 보였고, 기존의 스펙트럼 차감법은 musical noise의 영향으로 인해 상대적으로 다른 방식에 비해 합성음의 음질이 많이 떨어짐을 확인할 수 있었다.

• Proceedings of the Acoustical Society of Korea Conference
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• 1998.06e
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• pp.289-292
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• 1998

본 논문에서는 CELP 음성 부호화기의 성능을 향상시키는 방법을 제안한다. 제안된 방법은 최적 코드북 검색 과정에서 추가적인 알고리듬의 지연 없이 미래 정보를 이용하고 두 인접한 코드북 부프레임 사이의 동시 최적화를 통하여 음성 부호화기의 성능을 향상시킨다. 또한, 제안된 코드북 검색 과정의 계산량을 조절하기 위한 방법도 제공된다. 제안된 방법의 성능을 검증하기 위하여 IS-96A QCELP 음성 부호화기를 이용하여 합성음의 스펙트럼과 Segmental SNR로 성능을 측정하는 모의실험을 실시하였으며, 제안된 방법을 적용한 QCELP 음성 부호화기가 기존의 QCELP에 비하여 향상된 성능을 보여주었다.

• Proceedings of the IEEK Conference
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• 2000.11b
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• pp.188-191
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• 2000

This paper presents a register scheduling and allocation algorithm for high level synthesis. The proposed algorithm executes the low power scheduling to reduce the switching activity using shut down technique which was not unnecessary the calculation through the extraction DFG from VHDL description. Also, the register allocation algorithm determines the minimum register after the life time analysis of all variable. It is minimum the switching activity using graph coloring technique for low power consumption. The proposed algorithm proves the effect through various filter benchmark to adopt a new scheduling and allocation algorithm considering the low power.

• Journal of the Korean Institute of Telematics and Electronics A
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• v.31A no.12
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• pp.122-134
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• 1994

Design of a heuristic algorithm for high level synthesis of multichip architecture is presented in this paper. Considering the design constraints: individual chip area, I/O pin counts, chip-to-chip interconnection counts, interchip communication delay, and chip latecy, the proposed system automatically generates pipelined multichip architectures from behavioral descriptions. For efficient mulichip synthesis, a new methodology is proposed, which performs partitioning and schedulting of SFG into multichip architectures simultaneously. Experimental results for several benchmark programs show that the systems can be used for designing multichip hardware efficiently.

• Proceedings of the Korean Institute of Intelligent Systems Conference
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• 2000.11a
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• pp.99-101
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• 2000

DNA 컴퓨팅 기법은 실제 생체 분자(bio-molecule)를 계산의 도구로 사용하는 새로운 계산 방법으로, 진화 연산과 결합하여 인공지능의 새로운 분야로 부각되고 있다. 그러나, 실제 생체 분자를 계산의 도구로 사용하기 때문에 기존의 컴퓨터에 적용하기 어렵고, 단순히 합성과 분리라는 간단한 방법으로 해를 구하기 때문에 보다 효과적인 알고리즘을 개발하여야 할 필요성이 있다. 따라서, 본 논문에서는 DNA 컴퓨팅 기법을 컴퓨터에 적용하기 위한 방법으로 DNA 컴퓨팅에서의 코드 합성 기법과 유전자 알고리즘을 이용하여 NP-complete 문제중의 하나인 Sub-Set Sum 문제를 해결하여 그 결과를 분석한다. Sub-Set Sum 문제에서 단순 유전자 알고리듬보다 DNA 코드 유전자 알고리즘이 높은 성능을 보인다.