• The Journal of Sustainable Design and Educational Environment Research
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• v.12 no.2
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• pp.31-42
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• 2013

The purpose of this study was to analyze the school location decision factor with land use planning and urban design. And this research proposed the school location decision factor for urban amenity. This research proved the fact that the school land correlated with the park, the other school land etc. And this result will be used in decision-making-process of land use planning, public land development construction oriental, urban design and city policy.

• Proceedings of the Korea Water Resources Association Conference
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• 2016.05a
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• pp.482-486
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• 2016

광주광역시 도심유역의 14개 단위유역(영본B02~영본B25)으로 면적 $501.19km^2$ 중 약 42%에 해당하는 $211.86km^2$을 대상유역으로 분산식 빗물관리에 의한 물순환 체계를 구축하였다. 지목별 저감대상 면적은 대지, 창고, 공장용지는 전체면적의 15%, 주유소, 학교, 잡종지, 종교용지, 주차장은 5%, 도로는 10%를 적용하여 저감대상 산출면적은 $9.1km^2$로 설정하였으며, 초기강우 10mm에 대한 초기강우유출량 $90,885m^2$이 발생하며 이는 각 단위유역의 토지이용별로 침투통, 침투측구, 침투화분, 침투도랑, 수목여과박스, 식생수로, 빗물저금통, 투수블럭의 8개 시설에 의해 침투 및 저류하는 것을 제안하였으며, 또한, 본 연구의 대상유역에서 발생하는 비점오염원 발생부하량은 8,439.16kg/일으로 그 중 2.4%에 해당하는 210.186kg/일이 본 연구에서 제안한 빗물 관리시설에 의해서 삭감되는 것으로 분석되었다. 또한, 빗물관리시설의 총 투자비용은 약 322억원이며, 효과 비용은 343억원으로 산정되었다.

• Journal of the Korea Institute of Information Security & Cryptology
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• v.11 no.1
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• pp.64-72
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• 2001

This paper is on a design of the high-speed cipher IC using IDEA algorithm. The chip is consists of six functional blocks. The principal blocks are encryption and decryption key generator, input data circuit, encryption processor, output data circuit, operation mode controller. In subkey generator, the design goal is rather decrease of its area than increase of its computation speed. On the other hand, the design of encryption processor is focused on rather increase of its computation speed than decrease of its area. Therefore, the pipeline architecture for repeated processing and the modular multiplier for improving computation speed are adopted. Specially, there are used the carry select adder and modified Booth algorithm to increase its computation speed at modular multiplier. To input the data by 8-bit, 16-bit, 32-bit according to the operation mode, it is designed so that buffer shifts by 8-bit, 16-bit, 32-bit. As a result of simulation by 0.25 $\mu\textrm{m}$ process, this IC has achieved the throughput of 1Gbps in addition to its small area, and used 12,000gates in implementing the algorithm.