• Title/Summary/Keyword: 하드차인

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A study of mitigated interference Chaotic-OOK system in IEEE802.15.4a (IEEE 802.15.4a 채널환경하에서의 저간섭 Chaotic OOK 무선통신기술의 BER 성능분석에 관한 연구)

  • Jeong, Jae-Ho;Park, Goo-Man;Jeon, Tae-Hyun;Seo, Bo-Seok;Kwak, Kyung-Sup;Jang, Yeong-Min;Choi, Sang-Yule;Cha, Jae-Sang
    • Journal of Broadcast Engineering
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    • v.12 no.2
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    • pp.148-158
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    • 2007
  • Recently, IEEE 802.15.4a(low-rate UWB) technique has been paid much attention to the LR-UWB communication system for WPAN. However, there are various interferences such as MPI(Multi Path Interference) or IPI(Inter Piconet Interference) in IEEE 802.15.4a wireless channel. In order to cancel various interferences occurred to WPAN environment, in this paper, we propose a UWB wireless communication system with high QoS(Quality of Service) which is a chaotic-OOK(On-Off Keying) system using unipolar ZCD(Zero Correlation Duration) spreading code in physical layer level. Furthermore, we analyze its performance via simulations and verify the availability of proposed system with prototype implementation.

An Empirical Study on Defense Future Technology in Artificial Intelligence (인공지능 분야 국방 미래기술에 관한 실증연구)

  • Ahn, Jin-Woo;Noh, Sang-Woo;Kim, Tae-Hwan;Yun, Il-Woong
    • Journal of the Korea Academia-Industrial cooperation Society
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    • v.21 no.5
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    • pp.409-416
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    • 2020
  • Artificial intelligence, which is in the spotlight as the core driving force of the 4th industrial revolution, is expanding its scope to various industrial fields such as smart factories and autonomous driving with the development of high-performance hardware, big data, data processing technology, learning methods and algorithms. In the field of defense, as the security environment has changed due to decreasing defense budget, reducing military service resources, and universalizing unmanned combat systems, advanced countries are also conducting technical and policy research to incorporate artificial intelligence into their work by including recognition systems, decision support, simplification of the work processes, and efficient resource utilization. For this reason, the importance of technology-driven planning and investigation is also increasing to discover and research potential defense future technologies. In this study, based on the research data that was collected to derive future defense technologies, we analyzed the characteristic evaluation indicators for future technologies in the field of artificial intelligence and conducted empirical studies. The study results confirmed that in the future technologies of the defense AI field, the applicability of the weapon system and the economic ripple effect will show a significant relationship with the prospect.

Fixed-Point Modeling and Performance Analysis of a SIFT Keypoints Localization Algorithm for SoC Hardware Design (SoC 하드웨어 설계를 위한 SIFT 특징점 위치 결정 알고리즘의 고정 소수점 모델링 및 성능 분석)

  • Park, Chan-Ill;Lee, Su-Hyun;Jeong, Yong-Jin
    • Journal of the Institute of Electronics Engineers of Korea SD
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    • v.45 no.6
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    • pp.49-59
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    • 2008
  • SIFT(Scale Invariant Feature Transform) is an algorithm to extract vectors at pixels around keypoints, in which the pixel colors are very different from neighbors, such as vortices and edges of an object. The SIFT algorithm is being actively researched for various image processing applications including 3-D image constructions, and its most computation-intensive stage is a keypoint localization. In this paper, we develope a fixed-point model of the keypoint localization and propose its efficient hardware architecture for embedded applications. The bit-length of key variables are determined based on two performance measures: localization accuracy and error rate. Comparing with the original algorithm (implemented in Matlab), the accuracy and error rate of the proposed fixed point model are 93.57% and 2.72% respectively. In addition, we found that most of missing keypoints appeared at the edges of an object which are not very important in the case of keypoints matching. We estimate that the hardware implementation will give processing speed of $10{\sim}15\;frame/sec$, while its fixed point implementation on Pentium Core2Duo (2.13 GHz) and ARM9 (400 MHz) takes 10 seconds and one hour each to process a frame.

IPv6 기반의 정보 공유 P2P 개발

  • 이재준;김유정;안철현;이영로
    • Proceedings of the Korean Operations and Management Science Society Conference
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    • 2003.05a
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    • pp.21-27
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    • 2003
  • 분산컴퓨팅, 다자간 협업, 대용량 고품질의 컨텐츠 교환을 지원하는 P2P는 차세대 인터넷의 핵심 어플리케이션이 될 것이다. 본래 인터넷의 근본이었던 IP 라우팅도 P2P 방식이었다. 장비가 다양해지고, PC가 증가하게 됨에 따라 동적 IP를 사용하거나, 하나의 IP를 여러 사람이 공유하여 사용하는 복잡한 방식을 취하기 시작했다. 그러나 새로운 IP 주소들이 충분히 공급될 수 있다면, 하나의 장치 당 하나의 주소 체제가 다시 각광을 받게 될 것이고, 지금처럼 불규칙적인 동적 IP 주소를 활용하지 않아도 될 것이다. 그런 의미에서 IPv6는 풍부한 주소자원을 각 단말에 부여할 수 있어, IPv16 기반의 P2P 구축은 P2P의 성능을 최적화하는 방법이 될 것이다. 현재 P2P는 콘텐츠 공유 및 전달, 네트워크/장치(하드디스크, CPU) 리소스 공유, 다자간 원격협업, 검색, 호스팅 및 프로젝트 관리 등 다양한 방법으로 활용되고 있다. 2000년경부터 대두되기 시작한 P2P 애플리케이션은 지난 2년 동안 급속하게 늘어났으며, 특히 인터넷 사용자들은 컨텐츠를 공유/전달할 목적으로 P2P를 많이 사용하고있다. 그러나 컨텐츠의 공유에 있어 MP3, 동영상, 이미지의 전달 및 공유에 그치고 있어, P2P를 기업 환경에서 지식공유 및 전달을 위한 시스템으로 활용하는 경우는 아직 미약하다. 그러므로 본 논문에서는 조직 내에서 정보활용 능력을 제고하기 위한 방안으로 P2P 시스템을 정보 공유 시스템으로 팔용하고, P2P의 성능을 최적화 할 수 있는 IPv6 기반의 개발 방안을 제안하고자 한다. 본 IPv6 기반의 정보 공유 P2P는 IPv6 전문가 그룹을 통해 시범적으로 적응하는 것으로 시작해, 학교 및 연구소를 통한 정보지식 공유 그리고 기업 정보화 솔루션으로 활용 될 수 있다.을 제시한다. 이렇게 함으로써 최대한 고객 납기를 만족하도록 계획을 수립할 수 있게 된다. 본 논문에서 제시하는 계획 모델을 사용함으로써 고객 주문에 대한 대응력을 높일 수 있고, 계획의 투명성으로 인한 전체 공급망의Bullwhip effect를 감소시킬 수 있는 장점이 있다. 동시에 이것은 향후 e-Business 시스템 구축을 위한 기본 인프라 역할을 수행할 수 있게 된다. 많았고 년도에 따른 변화는 보이지 않았다. 스키손상의 발생빈도는 초기에 비하여 점차 감소하는 경향을 보였으며, 손상의 특성도 부위별, 연령별로 다양한 변화를 나타내었다.해가능성을 가진 균이 상당수 검출되므로 원료의 수송, 김치의 제조 및 유통과정에서 병원균에 대한 오염방지에 유의하여야 할 것이다. 확인할 수 있었다. 이상의 결과에 의하면 고농도의 유기물이 함유된 음식물쓰레기는 Hybrid Anaerobic Reactor (HAR)를 이용하여 HRT 30일 정도에서 충분히 직접 혐기성처리가 가능하며, 이때 발생된 $CH_{4}$를 회수하여 이용하면 대체에너지원으로 활용 가치가 높은 것으로 판단된다./207), $99.2\%$(238/240), $98.5\%$(133/135) 및 $100\%$ (313)였다. 각각 두 개의 요골동맥과 우내흉동맥에서 부분협착이나 경쟁혈류가 관찰되었다. 결론: 동맥 도관만을 이용한 Off pump CABG를 시행하여 감염의 위험성을 증가시키지 않으면서 영구적인 신경학적 합병증을 일으키지 않았고 좋은 혈관 개존율을 보여주었다. 따라서 동맥 도관을 이용한 Off pump CABG는 관상동맥의 협착의 정도에 따라 효율적으로 시행 시 좋은 임상결과를 얻을 수 있을 것으로 생각된다.였다. 그러나 심근 기능이나

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ASIC Design of Lifting Processor for Motion JPEG2000 (Motion JPEG2000을 위한 리프팅 프로세서의 ASIC 설계)

  • Seo Young-Ho;Kim Dong-Wook
    • The Journal of Korean Institute of Communications and Information Sciences
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    • v.30 no.5C
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    • pp.344-354
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    • 2005
  • In this paper, we proposed a new lifting architecture for JPEG2000 and implemented to ASIC. We proposed a new cell to execute unit calculation of lifting using the property of lifting which is the repetitious arithmetic with same structure, and then recomposed the whole lifting by expanding it. After the operational sequence of lifting arithmetic was analyzed in detail and the causality was imposed for implementation to hardware, the unit cell was optimized. A new lifting kernel was organized by expanding simply the unit cell, and a lifting processor was implemented for Motion JPEG2000 using it. The implemented lifting kernel can accommodate the tile size of $1024{\times}1024$, and support both lossy compression using the (9,7) filter and lossless compression using (5,3) filter. Also, it has the same output rate as input rate, and can continuously output the wavelet coefficients of 4 types(LL, LH, HL, HH) at the same time. The implemented lifting processor completed a course of ASIC using $0.35{\mu}m$ CMOS library of SAMSUNG. It occupied about 90,000 gates, and stably operated in about 150MHz though difference from the used macro cell for the multiplier. Finally, the improved operated in about 150MHz though difference from the used macro cell for the multiplier. Finally, the performance can be identified in comparison with the previous researches and commercial IPs.

A Modular Architecture and Its Procedure of Signalling at the NNI for B-ISDN in korea (국내 B-ISDN 망노드접면에서의 신호방식 모듈러 구조 및 절차)

  • Park, Nam-Hun;Min, Byeong-Do;Lee, Seok-Gi;Cha, Yeong-Uk;Kim, Sang-Ha
    • The Transactions of the Korea Information Processing Society
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    • v.4 no.2
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    • pp.531-542
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    • 1997
  • In this paper,we propose applicable methodology using simple scenarios for the architecture and its procedure of sibnalling at the NNI for B-ISDN in Korea.By the recent technologies,the flexible and intergrated networks of the future are designed, and the infrastructure hardware and software of those networks are sdsigned based on the modular concepts.Also the ATM-based B-ISDN must be able to support the broadband transmission function for providing various services with diverse bandwidths such as multimedia serivce and the function for controlling services and bandwidth is necessaty.Currently,the trquirements at the NNI for B-ISDN in korea atr based on the network mode connection type which is connection setup strucuture.They must show the upper/lower layer conformance to have the flexibility in new services and guarantee the interoperability between the network functions.But,network functions and protocol specifications described in this paper are limity to the first stage target system in korea.Therefore,we present the modular architecture which is corresponding to the B-ISUP of HAN/B-ISDN with those characteristics.Currently applicable architecture and procedure for B-ISUP and the functions of expandable modular architecture are also proposed.

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ASIC Design of Lifting Processor for Motion JPEG2000 (Motion JPEG2000을 위한 리프팅 프로세서의 ASIC 설계)

  • Seo Young-Ho;Kim Dong-Wook
    • The Journal of Korean Institute of Communications and Information Sciences
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    • v.30 no.7C
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    • pp.647-657
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    • 2005
  • In this paper, we proposed a new lifting architecture for JPEG2000 and implemented to ASIC. We proposed a new cell to execute unit calculation of lifting using the property of lifting which is the repetitious arithmetic with same structure, and then recomposed the whole lifting by expanding it. After the operational sequence of lifting arithmetic was analyzed in detail and the causality was imposed for implementation to hardware, the unit cell was optimized. A new lifting kernel was organized by expanding simply the unit cell, and a lifting processor was implemented for Motion JPEG2000 using it. The implemented lifting kernel can accommodate the tile size of 1024$\times$1024, and support both lossy compression using the (9,7) filter and lossless compression using (5,3) filter. Also, it has the same output rate as input rate, and can continuously output the wavelet coefficients of 4 types(LL, LH, HL, HH) at the same time. The implemented lifting processor completed a course of ASIC using 0.35$\mu$m CMOS library of SAMSUNG. It occupied about 90,000 gates, and stably operated in about 150MHz though difference from the used macro cell for the multiplier. Finally, the improved operated in about 150MHz though difference from the used macro cell for the multiplier. Finally, the performance can be identified in comparison with the previous researches and commercial IPs.

Log-Structured B-Tree for NAND Flash Memory (NAND 플래시 메모리를 위한 로그 기반의 B-트리)

  • Kim, Bo-Kyeong;Joo, Young-Do;Lee, Dong-Ho
    • The KIPS Transactions:PartD
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    • v.15D no.6
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    • pp.755-766
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    • 2008
  • Recently, NAND flash memory is becoming into the spotlight as a next-generation storage device because of its small size, fast speed, low power consumption, and etc. compared to the hard disk. However, due to the distinct characteristics such as erase-before-write architecture, asymmetric operation speed and unit, disk-based systems and applications may result in severe performance degradation when directly implementing them on NAND flash memory. Especially when a B-tree is implemented on NAND flash memory, intensive overwrite operations may be caused by record inserting, deleting, and reorganizing. These may result in severe performance degradation. Although ${\mu}$-tree has been proposed in order to overcome this problem, it suffers from frequent node split and rapid increment of its height. In this paper, we propose Log-Structured B-Tree(LSB-Tree) where the corresponding log node to a leaf node is allocated for update operation and then the modified data in the log node is stored at only one write operation. LSB-tree reduces additional write operations by deferring the change of parent nodes. Also, it reduces the write operation by switching a log node to a new leaf node when inserting the data sequentially by the key order. Finally, we show that LSB-tree yields a better performance on NAND flash memory by comparing it to ${\mu}$-tree through various experiments.

Double Threshold Method for EMG-based Human-Computer Interface (근전도 기반 휴먼-컴퓨터 인터페이스를 위한 이중 문턱치 기법)

  • Lee Myungjoon;Moon Inhyuk;Mun Museong
    • Journal of Biomedical Engineering Research
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    • v.25 no.6
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    • pp.471-478
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    • 2004
  • Electromyogram (EMC) signal generated by voluntary contraction of muscles is often used in a rehabilitation devices such as an upper limb prosthesis because of its distinct output characteristics compared to other bio-signals. This paper proposes an EMG-based human-computer interface (HCI) for the control of the above-elbow prosthesis or the wheelchair. To control such rehabilitation devices, user generates four commands by combining voluntary contraction of two different muscles such as levator scapulae muscles and flexor-extensor carpi ulnaris muscles. The muscle contraction is detected by comparing the mean absolute value of the EMG signal with a preset threshold value. However. since the time difference in muscle firing can occur when the patient tries simultaneous co-contraction of two muscles, it is difficult to determine whether the patient's intention is co-contraction. Hence, the use of the comparison method using a single threshold value is not feasible for recognizing such co-contraction motion. Here, we propose a novel method using double threshold values composed of a primary threshold and an auxiliary threshold. Using the double threshold method, the co-contraction state is easily detected, and diverse interface commands can be used for the EMG-based HCI. The experimental results with real-time EMG processing showed that the double threshold method is feasible for the EMG-based HCI to control the myoelectric prosthetic hand and the powered wheelchair.

AS B-tree: A study on the enhancement of the insertion performance of B-tree on SSD (AS B-트리: SSD를 사용한 B-트리에서 삽입 성능 향상에 관한 연구)

  • Kim, Sung-Ho;Roh, Hong-Chan;Lee, Dae-Wook;Park, Sang-Hyun
    • The KIPS Transactions:PartD
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    • v.18D no.3
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    • pp.157-168
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    • 2011
  • Recently flash memory has been being utilized as a main storage device in mobile devices, and flashSSDs are getting popularity as a major storage device in laptop and desktop computers, and even in enterprise-level server machines. Unlike HDDs, on flash memory, the overwrite operation is not able to be performed unless it is preceded by the erase operation to the same block. To address this, FTL(Flash memory Translation Layer) is employed on flash memory. Even though the modified data block is overwritten to the same logical address, FTL writes the updated data block to the different physical address from the previous one, mapping the logical address to the new physical address. This enables flash memory to avoid the high block-erase cost. A flashSSD has an array of NAND flash memory packages so it can access one or more flash memory packages in parallel at once. To take advantage of the internal parallelism of flashSSDs, it is beneficial for DBMSs to request I/O operations on sequential logical addresses. However, the B-tree structure, which is a representative index scheme of current relational DBMSs, produces excessive I/O operations in random order when its node structures are updated. Therefore, the original b-tree is not favorable to SSD. In this paper, we propose AS(Always Sequential) B-tree that writes the updated node contiguously to the previously written node in the logical address for every update operation. In the experiments, AS B-tree enhanced 21% of B-tree's insertion performance.