• The Journal of Korean Institute of Communications and Information Sciences
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• v.28 no.6A
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• pp.405-413
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• 2003

This paper presents new DSP (Digital Signal Processor) instructions and their hardware architecture to efficiently implement RS (Reed-Solomon) codecs, which is one of the most widely used FEC (Forward Error Control) algorithms. The proposed DSP architecture can implement various primitive polynomials by program, and thus, hardwired codecs can be replaced. The new instructions and their hardware architecture perform GF (Galois Field) operations using the proposed GF multiplier and adder. Therefore, the proposed DSP architecture can significantly reduce the number of clock cycles compared with existing DSP chips. It can perform RS decoding rate of up to 228.1 Mbps on 130MHz DSP chips.

• The Journal of Korean Institute of Communications and Information Sciences
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• v.14 no.4
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• pp.374-387
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• 1989

The decoding method of Binary BCH Codes using symmetric matrix is proposed in this paper. With this method, the error-locator-polynomial is composed by symmetric matrix which consists of the powers of the unknown X plus the synfromes as its elements. The symmetric matirx can also be represented in terms of the unknown X. But the each coefficients of the error-locator polynomial represents the matirx with the syndromes as its entries. By utilizing this proposed algorithm, the device for decoding circuit of the (63, 45) BCH Code for t=3 has been implemented for demonstration.

• Proceedings of the Korea Information Processing Society Conference
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• 2002.04b
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• pp.1293-1296
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• 2002

본 연구에서는 서브 스위치를 이용한 오류허용 정렬 네트워크를 제안한다. 기존의 정렬 네트워크에서는 여분의 경로와 네트워크의 복잡성문제가 있었다. 제안된 구조에서는 여분 경로를 확장시키기 위해서 각 스테이지마다 $\frac{N}{4}\sum\limits_{i=0}^{n=2}{(\frac{1}{2})}^i$ (N=입 출력수) 서브 스위치를 추가함으로써 여분의 경로가 $3^{n(n+1)/2}$만큼 증가하였다. 또한 제안된 정렬 네트워크는 기존의 네트워크의 이중 네트워크 plane 개념에서 사용한 스위치 소자와 링크 수와 비교해 볼 때 제안된 구조의 단일 plane을 이용한 구조가 복잡도에서 낮다. 결론적으로 제안된 서브 스위치를 이용한 오류 허용 정렬 네트워크는 여분의 경로를 증가시키면서 하드웨어적 복잡도를 감소시킬 수 있다.

• Proceedings of the Korean Society of Computer Information Conference
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• 2019.07a
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• pp.261-262
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• 2019

컨트롤러에 의해서 동작 및 운영되는 시스템들은 시스템의 내외부적인 요인으로 고장이 발생한 경우 정상적으로 작동할 수 없으며, 이 경우 2차 문제 발생 및 시스템 복구비용이 요구된다. 본 논문에서는 시스템 내부의 소프트웨어 오류 발생 시 컨트롤러 내의 감시 타이머를 사용하여 다운타임 시점 이전의 상태로 복구하는 알고리즘과, 하드웨어 오류의 경우 별도의 자동 리셋 기능을 통하여 시스템을 재설정하고 재 동작이 가능하도록 하는 기능을 구현한다. 제안 시스템은 시스템이 외부 지원 없이 자체적으로 반영구적인 동작이 가능하도록 함으로써, 시스템의 안정성과 신뢰성을 제공하고 운영 및 관리비용의 절감 효과를 제공한다.

• Journal of the Korea Academia-Industrial cooperation Society
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• v.12 no.4
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• pp.1889-1896
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• 2011

There has been a lot of researches to develop techniques that provide redundant paths, there by making Multistage Interconnection Networks(MINs) fault tolerant. So far, the redundant paths in MINs have been realized by adding additional hardware such as extra stages or duplicated data links. This paper presents a new MIN topology called Hierarchical MIN. The proposed MIN is constructed with 2.5N-4 switching elements, which are much fewer than that of the classical MINs. Even though there are fewer hardware than the classical MINs, the HMIN possesses the property of full access and also provides alternative paths for the fault tolerant. Furthermore, since there is the short cut in HMIN for the localized communication, it takes advantage of exploiting the locality of reference in multiprocessor systems. Its performance under varying degrees of localized communication is analysed and simulated.

• Journal of IKEEE
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• v.24 no.2
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• pp.502-506
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• 2020

With the development of autonomous driving technology, the importance of object recognition technology is increasing. Haze removal is required because the hazy weather reduces visibility and detectability in object recognition. However, the image from which the haze has been removed cannot properly reflect the unique color, and a detection error occurs. In this paper, we use CIE1931 color coordinate system to extend or reduce the color area to provide algorithms and hardware that reflect the colors of the real world. In addition, we will implement hardware capable of real-time processing in a 4K environment as the image media develops. This hardware was written in Verilog and implemented on the SoC verification board.

• Journal of IKEEE
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• v.23 no.4
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• pp.1288-1294
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• 2019

The channel-achieving property made the polar code show to advantage as an error-correcting code. However, sufficient error-correction performance shows the asymptotic property that is achieved when the length of the code is long. Therefore, efficient architecture is needed to realize the implementation of very-large-scale integration for the case of long input data. Although the most basic fully parallel encoder is intuitive and easy to implement, it is not suitable for long polar codes because of the high hardware complexity. Complementing this, a partially parallel encoder was proposed which has an excellent result in terms of hardware area. Nevertheless, this method has not been completely generalized and has the disadvantage that different architectures appear depending on the hardware designer. In this paper, we propose a hardware design scheme that applies the proposed systematic approach which is optimized for bit-dimension permutations. By applying this solution, it is possible to design a generalized partially parallel encoder for long polar codes with the same intuitive architecture as a fully parallel encoder.

• The Journal of the Korea institute of electronic communication sciences
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• v.17 no.1
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• pp.173-180
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• 2022

Approximate Computing is a promising method for designing hardware-efficient computing systems. Approximate multiplication is one of key operations used in approximate computing methods for high performance and low power computing. An approximate 4-2 compressor can implement hardware-efficient circuits for approximate multiplication. In this paper, we propose an approximate multiplier with low area and low power characteristics. The proposed approximate multiplier architecture is segmented into three portions; an exact region, an approximate region, and a constant correction region. Partial product reduction in the approximation region are simplified using a new 4:2 approximate compressor, and the error due to approximation is compensated using a simple error correction scheme. Constant correction region uses a constant calculated with probabilistic analysis for reducing error. Experimental results of 8×8 multiplier show that the proposed design requires less area, and consumes less power than conventional 4-2 compressor-based approximate multiplier.

• Journal of the Korea Institute of Information Security & Cryptology
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• v.24 no.1
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• pp.41-50
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• 2014

In this paper, we proposed an error detection in Gaussian normal basis multiplier over $GF(2^n)$. It is shown that by using parity prediction, error detection can be very simply constructed in hardware. The hardware overheads are only one AND gate, n+1 XOR gates, and one 1-bit register in serial multipliers, and so n AND gates, 2n-1 XOR gates in parallel multipliers. This method are detect in odd number of bit fault in C = AB.

• Proceedings of the Korean Institute of Information and Commucation Sciences Conference
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• 2001.10a
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• pp.648-651
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• 2001

This paper describes the 8-error-correction (204, 188) Reed-Solomon Decode. over GF(2$^{8}$ ) for a satellite communication. It is synthsized using a CMOS library. Decoding algorithm of Reed-Solomon codes consists of four steps which are to compute syndromes, to find error-location polynomial, to decide error-location, and to slove error-values. The decoder is designed using Modified Euclid algorithm in this paper. First of all, The functionalities of the circuit are verified through C++ programs, and then it is designed in Verilog HDL. It is verified through the logic simulations of each blocks. Finally, The Reed-Solomon Decoder is synthesized with Synopsys Tool.