• Title/Summary/Keyword: 플립침

검색결과 2건 처리시간 0.014초

Board Level Drop Simulations and Modal Analysis in the Flip Chips with Solder Balls of Sn-1.0Ag-0.5Cu Considering Underfill (언더필을 고려한 Sn-1.0Ag-0.5Cu 조성의 솔더볼을 갖는 플립칩에서의 보드레벨 낙하 및 진동해석)

  • Kim, Seong-Keol;Lim, Eun-Mo
    • Journal of the Korean Society of Manufacturing Technology Engineers
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    • 제21권2호
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    • pp.225-231
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    • 2012
  • Drop simulations of the board level in the flip chips with solder joints have been highlighted for years, recently. Also, through the study on the life prediction of thermal fatigue in the flip chips considering underfill, its importance has been issued greatly. In this paper, dynamic analysis using the implicit method in the Finite Element Analysis (FEA) is carried out to assess the factors effecting on flip chips considering underfill. The design parameters are size and thickness of chip, and size, pitch and array of solder ball with composition of Sn1.0Ag0.5Cu. The board systems by JEDEC standard is modeled with various design parameter combinations, and through these simulations, maximum yield stress and strain at each chip are shown at the solder balls. Modal analysis is simulated to find out the relation between drop impact and vibration of the board system.

Dynamic Reliability of Board Level by Changing the Design Parameters of Flip Chips (플립칩의 매개변수 변화에 따른 보드레벨의 동적신뢰성평가)

  • Kim, Seong-Keol;Lim, Eun-Mo
    • Journal of the Korean Society of Manufacturing Technology Engineers
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    • 제20권5호
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    • pp.559-563
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    • 2011
  • Drop impact reliability assessment of solder joints on the flip chip is one of the critical issues for micro system packaging. Our previous researches have been showing that new solder ball compositions of Sn-3.0Ag-0.5Cu has better mechanical reliability than Sn-1.0Ag-0.5Cu. In this paper, dynamic reliability analysis using Finite Element Analysis (FEA) is carried out to assess the factors affecting flip chip in drop simulation. The design parameters are size and thickness of chip, and size, pitch and array of solder ball with composition of Sn1.0Ag0.5Cu. The board systems by JEDEC standard including 15 chips, solder balls and PCB are modeled with various design parameter combinations, and through these simulations, maximum yield stress and strain at each chip are shown at the solder balls. It is found that larger chip size, smaller chip array, smaller ball diameter, larger pitch, and larger chip thickness have bad effect on maximum yield stress and strain at solder ball of each chip.