• Journal of the Korea Institute of Information and Communication Engineering
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• v.16 no.2
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• pp.273-278
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• 2012

In this contribution, we design and implement an SPI hardware interface for the microprocessor to communicate with the MMC (Multi-Media Card) in an embedded system. Proposed architecture is compatible with the APB in AMBA bus architecture. Embedding OS in an embedded system means a big burden in terms of hardware and software ending up with performance decline. In this paper, we adopt the concept of SPI communication without using OS in the embedded system and implement in a form of FPGA chip. The designed SPI module was automatically synthesized, placed, and routed. Implementation was performed through the Altera FPGA and well operated at 25MHz clock frequency, which satisfied our target speed.

• Proceedings of the Korean Information Science Society Conference
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• 2006.10b
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• pp.442-447
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• 2006

디지털 카메라의 대중화와 고용량 저장매체의 보편화로 인해 대중들은 손쉽게 디지털 사진 촬영이 가능하게 되었다. 디지털 사진은 필름 사진과 달리 촬영을 하는데 있어 비용이 들지 않을 뿐만 아니라 플래쉬 메모리의 증가로 인해 다수의 사진들을 촬영할 수 있게 되었으나 그만큼 많은 사진들을 관리하고 분류하는 것은 쉽지 않은 일이 되었다. 따라서 디지털 사진을 자동으로 분류하고 관리하는 기능은 중요한 과제가 되었지만, 현재까지 나온 방법들은 사진 내의 객체가 확대, 축소 및 이동하거나 배경이 바뀌는 영상에 있어서 정확한 유사도를 측정하여 분류하는데 어려움이 있었다. 본 논문에서는 이와 같은 어려움을 보완한 디지털 사진의 클러스터링 알고리즘을 제안한다. 입력영상을 그리드 형태로 나누어 각 블록별로 측정한 유사도 값을 바탕으로 클러스터링하며, 이때 디지털 사진 내에 포함되어 있는 촬영정보인 EXIF를 이용하여 입력 영상에 따라 적응적(adaptive)으로 그리드를 나누어 비교한다. 또한, 영상에 따라 각기 다른 색상의 분포 정도를 고려해 색상 가중치를 고려하여 사진을 비교함으로써, 영상의 고수준(high-level) 분석에서처럼 객체와 배경을 추출하여 따로 분리하지 않고도 객체의 배경이 다른 사진들을 저수준(low-level) 에서 분석이 가능토록 하였다. 제안한 방법으로 실험한 결과 객체의 크기 및 이동이나 배경에 큰 영향을 받지 않으면서 입력영상들을 클러스터링 할 수 있었다.

• The Journal of Korean Institute of Communications and Information Sciences
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• v.36 no.7B
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• pp.818-826
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• 2011

This paper proposes a novel FTL (Flash Translation Layer) algorithm employing sector-level mapping technique based on locality to reduce the number of erase operations in flash memory accesses. Sector-level mapping technique shows higher performance than other mapping techniques, even if it requires a large mapping table. The proposed algorithm reduces the size of mapping table by employing dynamic table update, processes sequential writes by exploiting sequential locality and extracts hot sector in random writes. Experimental results show that the number of erase operations has been reduced by 75.4%, 65.8%, and 10.3% respectively when compared with well-known BAST, FAST and sector mapping algorithms.

• Journal of the Korea Institute of Information and Communication Engineering
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• v.10 no.11
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• pp.2062-2068
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• 2006

In his paper, embedded system implementation for IEEE802.l1p based OFDM-DSRC is presented. After the IEEE802.11p physical layer specification is introduced and BER performance of the modem is evaluated by simulation, implementation aspects of the system such as system architecture, design method and implementation results are addressed. Implemented embedded system for the OFDM-DSRC communication consists of FPGA, flash memory, ARM9 CPU Core, peripherals, etc. from the results, it is shown that the implemented system operates well according to IEEE802.11p specification. It is expected that implemented embedded system shall be used for wireless communication system such as ITS application by enhancing system optimizing.

• Proceedings of the Korean Institute of Information and Commucation Sciences Conference
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• 2010.05a
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• pp.833-835
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• 2010

The SPARTAN-3E development kit is equipped with an FPGA which holds 500 thousand logic gates and a bus system platform using MicroBlaze microprocessor system. This kind of embedded systems can be used to gather information from sensor nodes and send over to the main server periodically through the network gateway, using the microprocessor-based embedded system, so that edlers living alone under sensor coverage can send their moving information and can be applied to get help in the event of emergency situations. In this paper, we designed a simple embedded system based on a CPU and flash memories using such FPGAs which can be used to monitor those elderlies living alone. The developed hardware system can be directly combined with the web-based elders-living-alone monitoring system, making the system more efficient.

• Journal of KIISE:Computing Practices and Letters
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• v.16 no.11
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• pp.1031-1040
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• 2010

Hash join is one of the core algorithms in databases management systems. If a hash join cannot complete in one-pass because the available memory is insufficient (i.e., hash table overflow), however, it may incur a few sequential writes and excessive random reads. With harddisk as the tempoary storage for hash joins, the I/O time would be dominated by slow random reads in its probing phase. Meanwhile, flash memory based SSDs (flash SSDs) are becoming popular, and we will witness in the foreseeable future that flash SSDs replace harddisks in enterprise databases. In contrast to harddisk, flash SSD without any mechanical component has fast latency in random reads, and thus it can boost hash join performance. In this paper, we investigate several important and practical issues when flash SSD is used as tempoary storage for hash join. First, we reveal the va patterns of hash join in detail and explain why flash SSD can outperform harddisk by more than an order of magnitude. Second, we present and analyze the impact of cluster size (i.e., va unit in hash join) on performance. Finally, we emperically demonstrate that, while a commerical query optimizer is error-prone in predicting the execution time with harddisk as temporary storage, it can precisely estimate the execution time with flash SSD. In summary, we show that, when used as temporary storage for hash join, flash SSD will provide more reliable cost estimation as well as fast performance.

• Journal of the Institute of Electronics Engineers of Korea CI
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• v.45 no.3
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• pp.47-57
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• 2008

Recently, energy-efficient NAND Flash memory of large volume is favored as next-generation storage for sensor nodes. So far, most sensor node file systems are based on NOR flash and few file systems are applicable to large NAND flash memory. Although it is required to develop new file systems taking account of the features of NAND flash memory, it is difficult to develop them mainly due to the limit of SRAM memory on sensor nodes. Sensor nodes support SRAM of $4{\sim}10$ KBytes only. In this paper, we designed and implemented a novel file system to support data-centric applications. To do this, we added EEPROM of 1 KBytes to store persistent file description data efficiently and devised a simple wear-leveling method. This reduces the number of page updates, resulting in reduction in energy use and increase in lifetime of sensor nodes.

• Proceedings of the Korean Vacuum Society Conference
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• 2010.08a
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• pp.191-192
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• 2010

높은 유전상수를 가지는 터널 장벽물질 들은 플래쉬메모리 및 나노 부유게이트 메모리 소자에서 터널의 두께 및 밴드갭 구조의 변형을 통하여 단일층의 $SiO_2$ 터널장벽에 비하여 동작속도를 향상시키고 누설전류를 줄이며 전하보존 특성을 높여줄 수 있다.[1-3] 본 연구에서는 $Al_2O_3/HfO/Al_2O_3$구조의 고 유전체 터널장벽을 사용하여 $WSi_2$ 나노입자를 가지게 되는 metal-oxide-semiconductor(MOS)구조의 커패시터를 제작하여 전기적인 특성을 확인하였다. p형 (100) Si기판 위에 $Al_2O_3/HfO/Al_2O_3$ (AHA)의 터널장벽구조를 원자층 단일 증착법을 이용하여 $350^{\circ}C$에서 각각 2 nm/1 nm/3 nm 두께로 증착시킨 다음, $WSi_2$ 나노입자를 제작하기 위하여 얇은 $WSi_2$ 박막을 마그네트론 스퍼터링법으로 3 - 4 nm의 두께로 증착시켰다. 그 후 $N_2$분위기에서 급속열처리 장치로 $900^{\circ}C$에서 1분간의 열처리과정을 통하여 AHA로 이루어진 터널 장벽위에 $WSi_2$ 나노입자들이 형성할 수 있었다. 그리고 초 고진공 마그네트론 스퍼터링장치로 $SiO_2$ 컨트롤 절연막을 20 nm 증착하고, 마지막으로 열 증기로 200 nm의 알루미늄 게이트 전극을 증착하여 소자를 완성하였다. 그림 1은 AHA 터널장벽을 이용한 $WSi_2$ 나노 부유게이트 커패시터 구조의 1-MHz 전기용량-전압 특성을 보여준다. 여기서, ${\pm}3\;V$에서 ${\pm}9\;V$까지 게이트전압을 점차적으로 증가시켰을 때 메모리창은 최대 4.6 V로 나타났다. 따라서 AHA의 고 유전체 터널층을 가지는 $WSi_2$ 나노입자 커패시터 구조가 차세대 비 휘발성 메모리로서 충분히 사용가능함을 보였다.

• Journal of KIISE:Software and Applications
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• v.37 no.11
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• pp.851-858
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• 2010

Most mobile devices use a NAND flash memory as their secondary memory. A compressed code of the firmware is stored in the NAND flash memory of mobile devices in order to reduce the size and the loading time of the firmware from the NAND flash memory to a main memory. In order to use a demand paging properly, a compressed code should be decompressed very quickly. The thesis introduces a new dictionary based compression algorithm for the fast decompression. The introduced compression algorithm uses a different method with the current LZ method by storing the "exclusive or" value of the two instructions when the instruction for compression is not equal to the referenced instruction. Therefore, the thesis introduces a new compression format that minimizes the bit operation in order to improve the speed of decompression. The experimental results show that the decoding time is reduced up to 5 times and the compression ratio is improved up to 4% compared to the zlib. Moreover, the proposed compression method with the fast decoding time leads to 10-20% speed up of booting time compared to the booting time of the uncompressed method.

• Journal of the Korea Institute of Information and Communication Engineering
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• v.9 no.3
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• pp.493-497
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• 2005

This paper is about the research of the User Agent implementation under wireless embedded environment, using SIP which is one of protocol components construct the VoIP system. The User Agent is made of the User Agent configuration block, the device thread block to control devices and the SIP stack block to process SIP messages. The device thread consists of the RTP thread and the sound lard device processing block. Futhermore, the SIP stack consist of the worker thread to process proxy events, the SIP transceiver and SIP thread to transfer and receive SIP messages. The H/W platform is a board included the Intel's XScale PXA255 processor, flash memory, SDRAM, Audio CODEC module and wireless LAN threough PCMCIA socket, furthermore a microphone and headphone is used by the audio 1/0. The system has embedded linux kernel 2.4.19. For embedded environment, the function of User Agent and SIP method is diminished. Finally, the resource of system could be reduced about $12.9\%$, compared to overall system resource, by minimizing peripherals control and excepting TCP.