• The Journal of Korea Institute of Information, Electronics, and Communication Technology
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• v.7 no.1
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• pp.40-44
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• 2014

A bridge resistance deviation-to-period (BRD-to-P) converter is presented for interfacing resistive biosensors. It consists of a linear operational transconductance amplifier (OTA) and a current-controlled oscillator (CCO) formed by a current-tunable Schmitt trigger and an integrator. The free running period of the converter is 1.824 ms when the bridge offset resistance is $1k{\Omega}$. The conversion sensitivity of the converter amounts to $3.814ms/{\Omega}$ over the resistance deviation range of $0-1.2{\Omega}$. The linearity error of the conversion characteristic is less than ${\pm}0.004%$.

• Proceedings of the Korean Information Science Society Conference
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• 2003.10a
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• pp.253-255
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• 2003

오늘날 많은 가전제품들은 다양화. 쌍방성, 효율성, 개방성등 정보화 시대의 주요 특징들과 접목되어 생산되고 있으며, 이중 모바일 제품군(Low End)은 각광받는 주류 제품이라 할 수 있다. 그러나 대부분의 모바일 제품들은 그 특성상 파일 시스템을 지원하지 못하고 있기에, 본 논문에서 모바일 제품의 운영체제로서 파일 시스템이 지원되지 않는 실시간 운영체제(RTOS- Real Time Operation System)를 선택하여 가상머쉰(VM-Virtual Machine)을 설계 및 구현하였다. 위의 지원을 위해 자바 클래스 파일을 C 언어 형태로 변환하여 VM 과 직접적으로 링크하는 방법인 프리링킹(Prelinking), 프리로딩(Preloading) 혹은 로마이징(ROMizing)이라고 알려져 있는 기법을 도입하였다.

• The Transactions of the Korean Institute of Electrical Engineers
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• v.43 no.6
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• pp.1001-1009
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• 1994

The present paper deals with a new developed sensor for measuring the time-varying magnetic fields and describes the experimental results of trasient magnetic field that takes place during the operations of electric appliance. The operation principle of the self-integrating magnetic field sensor by using coaxial cable is analyzed and a calibration investigation is carried out. The frequency bandwidth of the magnetic field measurement system is from 40 Hz to about 300 kHz. The magnetic field induced by the starting and/or operation of electric appliance mainly includes the odd harmonics such as the third, the fifth and the seventh harmonics. The magnetic field intensity caused during the operation of ultrasonic washer is inversely proportional to distance, this correspodns to induction component. As a result, it was known that the odd harmonics of magnetic field in the desing of electromagnetic shield employed for protecting electronic circuit and control devices have to be considered.

• Proceedings of the KIEE Conference
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• 1993.07a
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• pp.79-81
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• 1993

We have proposed a new technology compensating reactance component of line and load. Because capacity of SC is static, it is not appropriate to varing reactance and causes SSR problems. TCSC is introduced for the flecxible control of reactance of SC. If SC voltage is varied when the capacitor current is constant, it can be considered that capacity of SC was varied. SO capacity of SC can be controlled by controlling the voltage of SC. Control reference voltage of SC can be obtained from the condition that sum of reactive powers in all parts is zero.

• Proceedings of the Korea Information Processing Society Conference
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• 2009.11a
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• pp.425-426
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• 2009

본 논문은 차량형 네트워크에서 고급화된 루트 조회 요청의 응답시간을 측정하는 시뮬레이터를 구현하고 그 측정된 결과를 도시한다. 이산 이벤트 시뮬레이터에 기반하여 서버의 주기적 업데이트, 게이트웨이에서의 레코드당 리프레쉬, 차량으로부터의 조회 요청 발생 등의 사건들을 정의하고 이에 대한 동작을 구현한다. 시간 지역성을 대표하는 LRU 방식과 공간 지역성을 대표하는 FAR 방식의 성능을 측정하기 위해 참조시간을 기록하는 자료구조와 경위도 좌표를 거리로 변환하는 모듈을 작성하였으며 기존의 위치 이력 데이터로부터 조회 요청을 생성한다. 응답시간을 측정한 결과는 공간 지역성이 시간 지역성보다 응답시간에 더 많은 영향을 미치는 것으로 나타났으며 낮은 프리페치 부하에서 최대 4배 가량의 응답시간 차이를 보인다.

• The Journal of the Korea Contents Association
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• v.10 no.8
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• pp.73-83
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• 2010

This paper investigates protocol architecture of a Web-ZigBee gateway for interconnecting TCP/IP-based networks and ZigBee/IEEE802.15.4-based wireless sensor networks. The Web-ZigBee gateway delivers data between the TCP/IP network and the ZigBee network. Since those two networks have different communication protocols, a protocol translation mechanism is needed. Herein, we propose a method to deliver query messages from the Internet to the sensor network and receive data from sensors. The protocol translation is performed in the translation layer that is placed above the two application layers, i.e., the Internet application layer and ZigBee application layer. Among various interfaces, we use CGI programming to take care of translation functions efficiently. The CGI manages query information from a client on the Internet and data from the ZigBee sensor network. Whereas the TCP/IP enabled sensor network overlays two heterogeneous communication protocols, overlaying layers increase the complexity and cost of implementing the sensor network. On the contrary, the sensors in our gateway-based system are not only light (because each communication protocol works independently without overlaying), but also efficient because the translation layer mostly alleviates header overloading.

• Journal of the Korea Society of Computer and Information
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• v.12 no.5
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• pp.121-129
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• 2007

Scalarization is a process that a parallel construct like an array statement of Fortran 90 or FORALL of HPF is converted into sequential loops that maintain the correct semantics. Most compilers of HPF, recognized as a standard data parallel language, convert a HPF program into a Fortran 77 program inserted message passing primitives. During scalariztion, a parallel construct FORALL should be translated into Fortran 77 DO loops maintaining the semantics of FORALL. In this paper, we propose a scalarization algorithm which converts a FORALL construct into a DO loop with improved performance. For this, we define and use a relation distance vector to keep necessary dependence informations. Then we evaluate execution times of the codes generated by our method and by PARADIGM compiler method for various array sizes.

• Journal of the Institute of Electronics Engineers of Korea SD
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• v.41 no.8
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• pp.67-74
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• 2004

In this paper, a 3.3V 8-bit 500MSPS based on an interpolation architecture CMOS A/D converter is designed. In order to overcome the problems of high speed operation, a novel pre-amplifier, a circuit for the Reference Fluctuation, and an Averaging Resistor are proposed. The proposed Interpolation A/D Converter consists of Track ＆ Hold, four resistive ladders with 256 taps, 128 comparators, and digital blocks. The proposed A/D Converter is based on 0.35um 2-poly 4-metal N-well CMOS technology. The A/D Converter dissipates 440 mW at a 3.3 Volt single power supply and occupies a chip area of 2250um x 3080um.

• Proceedings of the Korea Information Processing Society Conference
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• 2004.11a
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• pp.757-760
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• 2004

유비쿼터스 시대의 도래에 발맞춰 유저가 콘텐츠를 이용하는 방법과 사용하는 기기는 PC에 머물지 않고 점차 다양화, 소형화 되고 있다. 최근, 많은 콘텐츠 중에서 e러닝 콘텐츠에 대한 관심은 높아지고 있으며, 본 논문에서는 e러닝 콘텐츠를 다양한 디바이스에 적합한 콘텐츠로 동적 변환하는 모듈을 제안한다. CC/PP 기반의 디바이스 프로파일과 사용자 정보를 포함한 유저 프로파일, 콘텐츠 구성정보를 가진 콘텐츠 프로파일을 통합하여 특성을 추상화 한다. 추상화 된 프로파일을 기반으로 변환방법을 생성하여 콘텐츠에 적용함으로서 해당 디바이스에 적합한 콘텐츠로 적응화 한다. 기존 HTML의 경우 잘 구성된(Well-formed)문서가 아닌 경우가 많고, 문서 내에 데이터와 구조정보를 모두 포함하고 있으므로, 요구되는 데이터의 추출과 정형화된 변환룰의 적용에 어려움이 따른다. 그 대안으로 본 적응화 모듈은 문서의 데이터와 표현 구조를 분리 할 수 있는 XML/XSL 기반의 콘텐츠를 대상으로 하고 있으며, e러닝 콘텐츠의 특성에 적합한 콘텐츠 프리패치 및 캐시 기법을 적용하여 콘텐츠 동적변환에 따른 응답시간 오버헤드를 최소화 하였다.

• Journal of the Institute of Electronics and Information Engineers
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• v.52 no.12
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• pp.99-108
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• 2015

The embedded microcontroller which is operated by the logic gates synchronized on the clock pulse, is gradually used as main controller of mission-critical systems. Severe electrical situations such as high voltage/frequency surge may cause malfunctioning of the clock source. The tolerant system operation is required against the various external electric noise and means the robust design technique is becoming more important issue in system clock failure problems. In this paper, we propose on-chip backup clock change architecture for the automatic clock failure detection. For the this, we adopt the edge detector, noise canceller logic and glitch-free clock changer circuit. The implemented edge detector unit detects the abnormal low-frequency of the clock source and the delay chain circuit of the clock pulse by the noise canceller can cancel out the glitch clock. The externally invalid clock source by detecting the emergency status will be switched to back-up clock source by glitch-free clock changer circuit. The proposed circuits are evaluated by Verilog simulation and the fabricated IC is validated by using test equipment electrical field radiation noise