• Journal of KIISE
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• v.42 no.10
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• pp.1280-1285
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• 2015

Many hardware-based regular expression matching architectures are proposed for high performance matching. In particular, regular expression processors such as ReCPU and SMPU perform pattern matching in a similar approach to that used in general purpose processors, which provide the flexibility when updating patterns. However, these processors are inefficient in performing class matching since they do not provide character class matching capabilities. This paper proposes an instruction set and architecture of a regular expression matching processor, which can support character class matching. The proposed processor can efficiently perform character class matching since it includes character class, character range, and negated character class matching capabilities.

• Journal of KIISE:Computer Systems and Theory
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• v.28 no.1_2
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• pp.1-10
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• 2001

본 논문에서는 부쉬 트리를 할당 트리로 변환한 후 결합 연산을 수행하면서 실제 실행시간을 동적으로 계산하고 그 결과에 의해 실시간에 프로세서를 할당하는 동적 프로세서 할당 기법을 이용한 파이프라인 해쉬 결합 알고리즘을 제안하였다. 프로세서를 할당하는 과정에서 초기 릴레이션의 기본 정보만을 이용하여 미리 프로세서를 할당하는 기존의 정적 프로세서 할당 기법은 정확한 실행시간을 예측할 수 없었다. 따라서 본 논문에서는 할당 트리 각 노드의 실행결과를 포함한 결합 과정 중의 정보를 다음 노드의 실행시간에 충분히 반영하는 동적 프로세서 할당 기법을 제안하였으며, 이로써 프로세서를 효율적으로 분배하고 전체적인 실행시간을 최소화하였다. 또한 전체적인 질의 실행시간을 줄이기 위하여 결합 가능성이 없는 튜플들을 제거한 후 결합 연산을 수행할 수 있도록 해쉬 필터 기법을 이용하였다. 결합 연산을 수행하기에 앞서 모든 결합 속성 값에 대해 해쉬 필터를 생성하는 정적 필터 기법은 모든 결합 연산의 중간 결과로 발생할 수 있으나 최종 결과 릴레이션의 튜플이 될 수 없는 튜플들까지도 모두 추출이 가능하다. 따라서 각각의 결합 연산 직전에 해쉬 필터를 생성하는 동적 필터 기법에 비해 결합 가능성이 없는 튜플을 최대한 제거할 수 있으며 이로써 결합 연산의 실행비용을 크게 줄일 수 있었다.

• The Journal of the Institute of Internet, Broadcasting and Communication
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• v.12 no.3
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• pp.9-13
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• 2012

In order to overcome the complexity and power problems of superscalar processors, the multi-core architecture has been prevalent recently. Although the execution-driven simulation is wide spread, the trace-driven simulation has speed advantages over the execution-driven simulation. We present a methodology to simulate multi-core architecture using trace-driven simulator. Using SPEC 2000 benchmarks as input, the trace-driven simulation has been performed for the cores ranging from 2 to 16 extensively. As a result, the 16-core processor resulted in 4.1 IPC and 13.3 times speed up over single-core processor on the average.

• The Journal of Korean Institute of Communications and Information Sciences
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• v.27 no.5C
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• pp.512-521
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• 2002

Recently, conventional superscalar RISC processors arrive their performance limit, and many researches on the next-generation architecture are concentrated on SMT(Simultaneous Multi-Threading). In SMT processors, multiple threads are executed simultaneously and share hardware resources dynamically. In this case, it is more important to supply instructions from multiple threads to processor core efficiently than ever. Because SMT architecture shows higher IPC(Instructions per cycle) than superscalar architecture, performance is influenced by fetch bandwidth and the size of fetch queue. Moreover, to use TLP(Thread Level Parallelism) efficiently, fetch thread selection algorithm and fetch bandwidth for each selected threads must be carefully designed. Thus, in this paper, the performance values influenced by these factors are analyzed. Based on the results, an optimal instruction fetch strategy for SMT processors is proposed.

• The Journal of the Institute of Internet, Broadcasting and Communication
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• v.14 no.3
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• pp.163-169
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• 2014

Recently, the importance of multicore processor system is growing rapidly. Multicore processors are classified either as symmetric or asymmetric. Asymmetric multicore processors consist of a high performance complex core and number of low performance simple cores, and are known to be more efficient than symmetric multicore processors. Therefore, performance impact on various configurations of asymmetric multi-core processor needs to be studied. Using SPEC 2000 benchmarks as input, the trace-driven simulation has been performed for different asymmetric quad-core and octa-core processors and compared to the corresponding symmetric ones.

• Proceedings of the Korean Society of Broadcast Engineers Conference
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• 2013.11a
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• pp.161-164
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• 2013

본 논문에서는 다양한 멀티미디어 코덱을 고속으로 처리하기 위하여 전용하드웨어가 아닌 병렬 어레이 프로세서 기반의 U-Chip(Universal-Chip) 구조를 제안하고 TSMC 80nm 공정을 사용하여 11,865,090개의 게이트 수를 가지는 칩으로 개발하였다. U-Chip은 역양자화(IQ), 역변환(IT), 움직임 보상(MC) 연산을 위한 $4{\times}16$ 개의 프로세싱 유닛으로 구성된 병렬 어레이 프로세서와 문맥적응적 가변길이디코딩(CAVLC)을 위한 비트스트림 프로세서와 인트라 예측(IP), 디블록킹필터(DF) 연산을 위한 순차 프로세서와 DMAC의 데이터 전송 및 각 프로세서를 제어하여 병렬 파이프라인 스케쥴링을 처리하는 시퀀서 프로세서 등으로 구성된다. 1개의 프로세싱 유닛에 1개의 매크로블록 데이터를 맵핑하여 총 64개의 매크로블록을 병렬처리 하였다. 64개 매크로블록의 대용량 데이터 전송 시간과 각 프로세서들의 연산을 동시에 병렬 파이프라인 함으로서 전체 연산 성능을 높일 수 있는 이점이 있다. 병렬 파이프라인 구조의 H.264 디코더 프로그램을 개발하였고 제작된 U-Chip을 통해 $720{\times}480$ 크기의 베이스라인 프로파일 영상에 대하여 코어 192MHz 동작, DDR 메모리 96MHz 동작에서 30fps의 처리율을 가짐을 확인하였다.

• KIISE Transactions on Computing Practices
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• v.23 no.2
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• pp.97-103
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• 2017

Many hardware-based regular expression matching architectures have been proposed for high-performance matching. In particular, regular expression processors, which perform pattern matching by treating the regular expressions as the instruction sequence like general purpose processors, have been proposed. After instruction sequence and data are provided in the instruction memory and data memory, respectively, a regular expression processor can perform pattern matching. To use a regular expression processor as a coprocessor, we need the host interface to transfer the instruction and data into the memory of a regular expression processor. In this paper, we design and implement the host interface between a host and a regular expression processor in the DE1-SoC board and the application program interface. We verify the operations of the host interface and a regular expression processor by executing the application programs which perform pattern matching using the application program interface.

• Journal of the Institute of Electronics Engineers of Korea SD
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• v.42 no.6 s.336
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• pp.67-74
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• 2005

Crypto-systems have difficulties in designing hardware due to the various standards. We propose a programmable and configurable architecture for cryptography coprocessors to accommodate various crypto-systems. The proposed architecture has a 32 bit I/O interface and internal bus width, and consists of a programmable finite field arithmetic unit, an input/output unit, a register file, and a control unit. The crypto-system is determined by the micro-codes in memory of the control unit, and is configured by programming the micro-codes. The coprocessor has a modular structure so that the arithmetic unit can be replaced if a substitute has an appropriate 32 bit I/O interface. It can be used in many crypto-systems by re-programming the micro-codes for corresponding crypto-system or by replacing operation units. We implement an elliptic curve crypto-processor using the proposed architecture and compare it with other crypto-processors

• Journal of the Korea Institute of Information and Communication Engineering
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• v.9 no.6
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• pp.1211-1217
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• 2005

Current generation embedded systems are built around only a small number of SOCs, which are again based on general-purpose embedded micro-processors, such as ARM and MIPS. These RISC-based processors are not, however, designed for specific functions such as networking and multimedia processing, whose importances have increased dramatically in recent years. Network devices for small business and home networks, are especially dependent upon such SOCs based on general processors. Except for PHY and MAC layer functions, which are built with hardware, all the network functions are processed by the embedded micro-processor. Enabling technologies such as VDSL and FTTH promise Internet access with a much higher speed, while at the same time explore the limitations of general purpose microprocessors. In this paper we design a network processor, embed it into an SOC for Home gateway, evaluate the performance rigorously, and gauge a possibility for commercialization.

• Aerospace Engineering and Technology
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• v.10 no.2
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• pp.105-113
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• 2011

During the development of flight software, the processor emulator and satellite simulator are essential tools for software development and verification, which can be substituted for the actual hardware. LEO satellites being developed by KARI recently use the MCM-ERC32SC processor for on-board computer (OBC). For the flight software (FSW) development and testing, the software-based spacecraft simulator was developed using TSIM-ERC32 processor emulator from Aeroflex Gaisler. It is needed to get rid of the constraints and dependencies of TSIM-ERC32 processor emulator and to obtain high performance processor emulator to develop full satellite simulator. This paper presents the development of the ERC32 emulator based on open source dynamic translator, QEMU, as the first step. And it describes the software development and testing/debugging on the developed emulator.