• Proceedings of the IEEK Conference
• /
• 1999.06a
• /
• pp.986-989
• /
• 1999

An 12bit current-mode folding and interpolation analog to digital converter (ADC) with multiplied folding amplifiers is proposed in this paper. A current - mode multiplied folding amplifier is employed not only to reduced the number of reference current source, but also to decrease a power dissipation within the ADC. The designed ADC fabricated by a 0.6${\mu}{\textrm}{m}$ n-well CMOS double metal/single poly process. The simulation result shows the power dissipation of 280㎽ with a power supply of 5V.

• Proceedings of the Korean Society of Precision Engineering Conference
• /
• 2003.10a
• /
• pp.190-190
• /
• 2003

동력 전달용 구동부품에 있어서 중공 플랜지 형상의 부품은 흔히 찾아 볼 수 있으며, 이는 높은 강도를 요구하기 때문에 강도향상을 위하여 단조에 의한 제품의 성형 방법이 많이 연구되고 있다. 중공 플랜지형상을 갖는 제품의 제조 방법으로서는 중실 플랜지 형상으로 단조하여 내경부를 절삭가공하는 방법, 중실 소재를 후방압출하여 중공 플랜지형상으로 단조하는 방법, 또는 중공의 초기소재를 사용하여 중공 플랜지형상으로 단조하는 방법이 일반적이다. 본 연구에서는 Fig. 1에 나타낸 것과 같이 중공 플랜지 형상을 갖는 기계 부품의 단조방법에 대해 연구하였으며, 중공 관의 내경을 $d^1$, 외경을 $d^2$, 플랜지부의 외경을 $D^0$, 중공 관의 두께를 t, 플랜지부의 두께를 T로 정의하였다. 중공 플랜지 형상에 있어서 공정 설계의 변수는 다양하겠으나, 본 연구에서는 중공관의 외경과 내경의 형상비 $\alpha$(=$d^2$/$d^1$), 플랜지의 폭과 중공관의 두께비 $\beta$(=B/t) 및 중공관의 두께와 플랜지의 두께비 r(=T/t)의 변화에 따른 성형조건에 관해 고찰하였다. 중공 플랜지 형상의 성형방법으로 Fig. 2에 나타낸 것과 같은 $\circled1$중실소재를 이용한 후방압출단조(backward extrusion forging)방법, $\circled2$중공 소재를 이용한 엎셋(upset forging)방법, $\circled3$중공 소재를 이용한 압조법(injection forging), $\circled4$중실소재를 이용한 압조-압출(injection-extruding forging)법의 4가지의 단조 방법을 제시 하였다. 또한, 유한요소해석을 수행하여 소성유동 형태, 유효변형률, 단조하중을 검토하고. 모델재료인 납을 이용한 실험을 통하여 이를 검증하였다. 이를 바탕으로 산업 현장에서 경험에 의존하였던 공정 설계를 보다 효과적으로 개선하기 위한 단조법을 제시하고자 하였다. 또한 중실 소재를 이용한 중공 플랜지 형상의 단조 방법 중 보다 적절한 단조방법인 압조 단조에 있어서 일반적으로 사용되고 있는 SM10C에 대한 유한요소 해석을 수행하였으며, 제품의 형상비에 따라 폴딩 결함의 발생 유무를 검토하고, 폴딩 결함 없이 단조하기 위한 중공 플랜지의 형상한계 비를 제시하였다.

• Journal of the Institute of Electronics Engineers of Korea SD
• /
• v.43 no.8 s.350
• /
• pp.19-26
• /
• 2006

In this paper, CMOS analog-to-digital converter (ADC) with a 6-bit 100MSPS at 1.8V is described. The architecture of the proposed ADC is based on a folding type ADC using resistive interpolation technique for low power consumption. Further, the number of folding blocks (NFB) is decreased by half of them compared to the conventional ones. A moebius-band averaging technique is adopted at the proposed ADC to improve performance. With the clock speed of 100MSPS, the ADC achieves an effective resolution bandwidth (ERBW) of 50MHz, while consuming only 4.5mW of power. The measured result of figure-of-merit (FoM) is 0.93pJ/convstep. The INL and DNL are within ${\pm}0.5 LSB$, respectively. The active chip occupies an area of $0.28mm^2$ in 0.18um CMOS technology.

• Convergence Security Journal
• /
• v.16 no.7
• /
• pp.113-120
• /
• 2016

This paper presents a new high-speed SHA-1 pipeline architecture having a computation delay close to the maximum critical path delay of the original SHA-1. The typical SHA-1 pipelines are based on either a hash operation or unfolded hash operations. Their throughputs are greatly enhanced by the parallel processing in the pipeline, but the maximum critical path delay will be increased in comparison with the unfolding of all hash operations in each round. The pipeline stage logics in the proposed SHA-1 has the latency is similar with the result of dividing the maximum threshold delay of a round by the number of iterations. Experimental results show that the proposed SHA-1 pipeline structure is 0.99 and 1.62 at the operating speed ratio according to circuit size, which is superior to the conventional structure. The proposed pipeline architecture is expected to be applicable to various cryptographic and signal processing circuits with iterative operations.

• Journal of the Korean Institute of Telematics and Electronics C
• /
• v.36C no.12
• /
• pp.20-26
• /
• 1999

A CMOS 6-bit 100MSPS ADC for DBS receiver is designed. The proposed ADC is composed of folding block, latch block, and digital block. The cascode interpolating block and kickback reduced latch are proposed with a high speed architecture. To verify the performance of ADC, simulations are carried out by HSPICE. The ADC achieves a clock frequency of 100MHz with a power dissipation of 40mW for 3 V supply voltage. The active chip area is $1500{\mu}m{\times}1000{\mu}m$with $0.65{\mu}m$ 2-poly 2-metal CMOS process. Further, INL and DNL are within ${\pm}0.6LSB$, ${\pm}0.5LSB$, respectively. SNDR is about 33dB at 10MHz input frequency.

• Journal of the Institute of Electronics Engineers of Korea SC
• /
• v.45 no.3
• /
• pp.51-58
• /
• 2008

This paper is a study of a prevention of power folding controller's thermal degradation. Power folding technology has been applied for many fields such as side rear vision mirror of vehicles, windshield wiper, antenna, power window. These controllers have been comprised with traditional DC moors, Switching electronic devices, and relays. But this methods have a limitation to overcome such problems of product reliability, endurance, noise margins. Therefore on this paper, to detect the movement of motor, sensing motor brush noise on a load sensing part has been used and controlling a precise RC timing control minimizes the thermal deterioration of motor. And using MOS FETs as a electronic switching device increases life-time and liability of control circuit. After testing such circuit and control method, repetition of operating time, cut-off time, wide operation voltage, power noise margin ware increased over eleven-fold.

• Journal of Gifted/Talented Education
• /
• v.22 no.3
• /
• pp.703-728
• /
• 2012

The purpose of this study was exploring instructive methods to make each gifted child's ability develop as more by selecting the dynamic method instead of existing static method in teaching and evaluating science-gifted students in elementary school and by analyzing conceptual change of electric circuit. In this research, 11 science-gifted students in primary school were chosen, and Dynamic Science Assessment(DSA) intended to comprehension of scientific electric circuit concept was performed as focusing on scaffolding aspects in order to find the transition process. And then, the features on transition process of students' concept were analyzed in quality. The results of the study were checked that the features of useful scaffolding input with respect to comprehending concepts of science gifted-students by using DSA. The less familiar to approach the subjects, the more presented numbers of scaffolding showed. As coming toward transition and same questions, scaffoldings (interactions) were declined because their level of transition was higher than before. Various ways were used in helping the students comprehend the concept on the method of connecting electric circuit and the emitting amount of current, which acted to adapt to daily life.

• The Journal of Korea Institute of Information, Electronics, and Communication Technology
• /
• v.10 no.2
• /
• pp.141-146
• /
• 2017

In this paper, a gradient magnitude hardware architecture based on hardware folding design method is proposed for low power image feature extraction. For the hardware complexity reduction, the projection vector chracteristic of gradient magnitude is applied. The proposed hardware architecture can be implemented with the small degradation of the gradient magnitude data quality. The FPGA implementation result shows the 41% of logic elements and 62% embedded multiplier savings compared with previous work using Altera Cyclone VI (EP4CE115F29C7N) FPGA and Quartus II v16.0 environment.

• The Research Journal of the Costume Culture
• /
• v.30 no.4
• /
• pp.513-528
• /
• 2022

The purpose of this study is to understand the concept of zero-waste design and to apply Sophia Vyzoviti's folding techniques to develop a zero-waste fashion design method that contributes to sustainable fashion design. In this study, we explore the method and characteristics of zero-waste fashion design based on the concept of folding described in Sophia Vyzoviti's book on folding techniques. Using the autonomy of Sophia Vyzoviti's folding technique, four changeable folding fashion designs were developed and produced, demonstrating zero-waste fashion design. The results were as follows. First, the development of fashion designs using Sophia Vyzoviti's folding techniques enabled the development and production of free and creative zero-waste fashion designs that were three-dimensional, continuous, fluid, and full of potential. Second, the production of zero-waste patterns was further developed into a transformable fashion design that can be used with geometric patterns. These folding techniques produced a fashion design method that could transform one piece of clothing, demonstration the potential for maintenance of creativity using a zero-waste design based on these folding techniques. Third, the double-faced fabric, Neoprene, was chosen as an appropriate material as it emphasizes the depth of folding with application of two colors and its cotton/polyester blend that is suitable for folding.

• Journal of The Korean Association For Science Education
• /
• v.27 no.4
• /
• pp.297-308
• /
• 2007

Inspired by the idea that classroom instruction proceeds through knowledge-sharing, this study examined different modes of knowledge-sharing that were realized in discursive practices in Korean secondary science classrooms. Data came from 9 science teachers. An interpretative strategy was employed to analyze the video-recording of the teachers' own science classrooms and transcriptions. The results showed four different modes of knowledge-sharing, including 'retrieving subject matter knowledge', 'reformulating subject matter knowledge', 'expansion and elaboration of understanding', and 'negotiation of meaning'. It was also revealed that there was a tie between an active mode of knowledge-sharing and scaffolding: the former allowed students to take active roles in discourses and the latter was one of the desired patterns of classroom interaction. It was suggested that further studies should be conducted to understand science instruction from more varied perspectives and to examine and utilize the detailed features of desired classroom practices like scaffolding.