• Title/Summary/Keyword: 패스스케줄 설계 시스템

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Pass Schedule Design for Improvement of Drawing Speed in the Dry Wire Drawing Process (신선 속도 향상을 위한 건식 신선 공정의 패스스케줄 설계)

  • 김영식;김동환;김병민;김민안;박용민
    • Proceedings of the Korean Society of Precision Engineering Conference
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    • 2000.11a
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    • pp.600-603
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    • 2000
  • In the high carbon steel wire drawing process, the wire temperature increases as the drawing speed is faster in order to increase the production rate in the shop floor. The rapid temperature rise causes the wire fracture in the dry wire drawing process. So, in this paper, the isothermal pass schedule program, which includes the calculation method of wire temperature at each pass, is proposed to prevent the wire fracture due to the temperature rise. Using the isothermal pass schedule program, it is newly proposed the pass schedule design system that prevents the cup-cone defects, improves the elongation of the final products and assures further deformation. As a result, the temperature rise of the wire was decreased and the production rate of the final product is remarkably grown up according to the increase of the final drawing speed than that of the conventional process. Also, the proposed pass schedule design system could give a useful information to the process designer who would design the high carbon steel wire drawing process.

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Real-time Full-duplex Ethernet Networks for Real-time Distributed Control System (실시간 분산 제어 시스템용 고속 전이중 이더넷 기반 통신망의 설계 및 성능 평가)

  • Choi, Jae-Young;Kim, Hyung-Seok;Kwon, Wook-Hyun;Lee, Sung-Woo;Song, Seong-Il
    • Proceedings of the KIEE Conference
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    • 2001.07d
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    • pp.2714-2716
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    • 2001
  • 본 논문에서는 일대일 전송에 국한되어 사용되는 전이중 패스트 이더넷 방식을 응용하여 고속 브로드 캐스팅 통신망을 구성하고 실시간 전송을 요구하는 데이터를 효율적으로 전달할 수 있는 알고리듬을 제시한다. 제안된 통신망의 세부구조와 통신망의 데이터 송수신 동작 등을 설명하고, 실시간 데이터 전송을 보장하기 위하여 실시간 메시지 스케줄링 알고리듬을 제시한다. 제시된 알고리듬을 적용하였을 때의 각종 시변수들에 대한 수학적인 분석을 통하여 실시간성 보장에 대한 성능평가를 포함한 통신망 성능 평가를 수행한다. 제안된 통신망 FER(Full-duplex Ethernet networks for Real-time communication)의 실제 구현 및 응용 대상에 대해서 언급한다.

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A SoC Design Synthesis System for High Performance Vehicles (고성능 차량용 SoC 설계 합성 시스템)

  • Chang, Jeong-Uk;Lin, Chi-Ho
    • The Journal of the Institute of Internet, Broadcasting and Communication
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    • v.20 no.3
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    • pp.181-187
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    • 2020
  • In this paper, we proposed a register allocation algorithm and resource allocation algorithm in the high level synthesis process for the SoC design synthesis system of high performance vehicles We have analyzed to the operator characteristics and structure of datapath in the most important high-level synthesis. We also introduced the concept of virtual operator for the scheduling of multi-cycle operations. Thus, we demonstrated the complexity to implement a multi-cycle operation of the operator, regardless of the type of operation that can be applied for commonly use in the resources allocation algorithm. The algorithm assigns the functional operators so that the number of connecting signal lines which are repeatedly used between the operators would be minimum. This algorithm provides regional graphs with priority depending on connected structure when the registers are allocated. The registers with connecting structure are allocated to the maximum cluster which is generated by the minimum cluster partition algorithm. Also, it minimize the connecting structure by removing the duplicate inputs for the multiplexor in connecting structure and arranging the inputs for the multiplexor which is connected to the operators. In order to evaluate the scheduling performance of the described algorithm, we demonstrate the utility of the proposed algorithm by executing scheduling on the fifth digital wave filter, a standard bench mark model.