• Journal of the Institute of Electronics Engineers of Korea SC
• /
• v.47 no.1
• /
• pp.29-34
• /
• 2010

This paper proposes a new parity-preserving reversible logic gate. It is a parity-preserving reversible logic gate, that is, the party of the outputs matches that of the inputs. In recent year, reversible logic gate has emerged as one of the important approaches for power optimization with its application in low CMOS design, quantum computing and nono-technology. We show that our proposed parity-preserving reversible logic gate is much better in terms of number of reversible logic gates, number of garbage-outputs and hardware complexity with compared ti the exiting counterpart.

• Proceedings of the IEEK Conference
• /
• 2003.07e
• /
• pp.2172-2175
• /
• 2003

본 논문에서는 DC 억압능력이 없거나 부족한 코드에 만족할 만한 DC 억압능력을 갖도록 하기 위한 멀티모드코드 방식을 제안한다. 제안한 멀티모드코드는 데이터열의 다중화를 위해 Pseudo Scrambling Technique를 사용하며, 다중화 된 데이터열의 변조를 위해 DC-free RLL(d, k) Code를 사용하는 특징을 가진다. 제안한 방법에서는 Sync 코드워드의 패리티를 다중화 정보로 사용하여 입력데이터를 2개의 데이터 열로 다중화하고, 2개로 다중화 된 데이터 열에 대해 DC-free RLL(d, k) Code를 사용하여 코드워드로 변환하며, 코드워드로 변환된 2 개의 코드워드 열에 대해 DC 성분이 적은 코드워드 열 하나를 선택하여 변조 스트림으로 출력한다. 본 논문에서는 Sync 코드워드의 패리티를 다중화 정보로 사용하여 별도의 Redundancy를 부가하지 않고 DC 억압성능을 향상시킬 수 있었다.

• Journal of the Institute of Electronics Engineers of Korea TC
• /
• v.49 no.8
• /
• pp.1-11
• /
• 2012

The multi-code spread spectrum communication system, which spreads data bit stream by multiplexing orthogonal codes, can transmit data in high rate. However it needs the high-cost good linear amplifier because of the multi-level output signal. In order to overcome this drawback several systems making the amplitude of output signal constant with Walsh codes have been proposed. Recently constant amplitude pre-coded multi-code spread spectrum systems using extended m-sequence have been proposed. In this paper we consider an extended m-sequence based constant amplitude multi-code spread spectrum system with code set partitioning. By grouping the orthogonal codes into 4 subsets, not only is the computational complexity of the transceiver reduced but BER performance also improves. It has been shown that parity checking on four detected codes at the receiver can correct code detection error and result in BER performance enhancement. In this paper we propose a improved parity check receiver. We carried out computer simulation to verify feasibility of the proposed algorithm.

• The Journal of Korean Institute of Communications and Information Sciences
• /
• v.38A no.9
• /
• pp.744-749
• /
• 2013

We propose soft user data input on LDPC codes with parity encoded by the (1, 7) run length limited (RLL) code for perpendicular magnetic recording channel. The user data are encoded by maximum transition run (MTR) (3;11) code. In order to minimize the loss of code rate, the (1, 7) RLL code only encode the parity of LDPC. Also, to increase performance, we propose only user data part applied soft output Viterbi algorithm (SOVA). The performance using the SOVA showed good performance lower than 26 dB. In contrast, it showed worse performance high than 26 dB. This is because of incorrect soft information by high jitter noise and two different input types for LDPC decoder.

• The Journal of Korean Institute of Communications and Information Sciences
• /
• v.23 no.5
• /
• pp.1149-1159
• /
• 1998

This paper presents the Controllable Self-Checking(CSC) Checker at which can be used the Fault-Tolerant System with the redundancy. According to the critical level of output(of system), especially, it can be instructed the time if it has to check the output or not. We adop the deterministic test, performed on-line, to detect the faults with a minimal test set. The results show the Parity 2-rail checker(P-TRC) which is designed much simpler than the checker has the higher fault coverage than the existent checker.

• The Journal of Korean Institute of Communications and Information Sciences
• /
• v.34 no.2C
• /
• pp.175-180
• /
• 2009

When we apply the LDPC code for high density optical storage channel, it is necessary to make an algorithm that the modulation code decoder must feed the LDPC decoder soft-valued information because LDPC decoder exploits soft values using the soft input. Therefore, we propose the soft-input soft-output run-length limited 17PP decoding algorithm and compare performance of LDPC codes. Consequently, we found that the proposed soft-input soft-output decoding algorithm using 17PP is 0.8dB better than the soft-input soft-output decoding algorithm using (1, 7) RLL.

• Journal of Broadcast Engineering
• /
• v.16 no.4
• /
• pp.635-646
• /
• 2011

In distributed video coding, low complexity encoder can be realized by shifting encoder-side complex processes to decoder-side. However, not only motion estimation/compensation processes but also complex LDPC decoding process are imposed to the Wyner-Ziv decoder, therefore decoder-side complexity has been one important issue to improve. LDPC decoding process consists of numerous iterative decoding processes, therefore complexity increases as the number of iteration increases. This iterative LDPC decoding process accounts for more than 60% of whole WZ decoding complexity, therefore it can be said to be a main target for complexity reduction. Previously, HDA (Hard Decision Aided) method is introduced for fast LDPC decoding process. For currently received parity bits, HDA method certainly reduces the complexity of decoding process, however, LDPC decoding process is still performed even with insufficient amount of parity request which cannot lead to successful LDPC decoding. Therefore, we can further reduce complexity by avoiding the decoding process for insufficient parity bits. In this paper, therefore, a parity request estimation method is proposed using bit plane-wise correlation and temporal correlation. Joint usage of HDA method and the proposed method achieves about 72% of complexity reduction in LDPC decoding process, while rate distortion performance is degraded only by -0.0275 dB in BDPSNR.

• Journal of Power System Engineering
• /
• v.8 no.1
• /
• pp.62-68
• /
• 2004

This paper describes a fault tolerant control in distributed PLC(Programmable Logic Controller) system to ensure reliability of controllers which have some faults simultaneously. First, the behavior of PLC is modeled as discrete expressions using Galois field. Then, we design the control laws for additional spare controllers to generate parity code with two dimensions. Finally, the algorithm for estimating normal output instead of abnormal output from the controllers with fault is suggested. Comparing to the traditional duplication method, the suggested method can reduce the number of spare controllers significantly to ensure control reliability. This method will be applied to an automatic system in order to increase reliability. Also, it can improve cost performance of the system.

• Journal of the Institute of Electronics Engineers of Korea CI
• /
• v.39 no.4
• /
• pp.19-27
• /
• 2002

We proposed an auto-tuning method of learning rate for performance improvement of backpropagation algorithm. Proposed method is used a fuzzy logic system for automatic tuning of learning rate. Instead of choosing a fixed learning rate, the fuzzy logic system is used to dynamically adjust learning rate. The inputs of fuzzy logic system are ${\Delta}$ and $\bar{{\Delta}}$, and the output is the learning rate. In order to verify the effectiveness of the proposed method, we performed simulations on a N-parity problem, function approximation, and Arabic numerals classification. The results show that the proposed method has considerably improved the performance compared to the backpropagation, the backpropagation with momentum, and the Jacobs' delta-bar-delta.

• Journal of the Korean Society for Aeronautical & Space Sciences
• /
• v.49 no.10
• /
• pp.879-882
• /
• 2021

The telemetry standard adopts SOQPSK-TG with excellent power and bandwidth efficiency as a modulation technique, and LDPC code with excellent performance as an error correction code. The SOQPSK-TG transmitter consists of a precoder and a CPM modulator. Rather than implementing each receiver separately, the reception performance is improved by combining the trellis and implementing it as a Viterbi decoder. In this paper, the reception performance of LDPC-encoded SOQPSK-TG was evaluated by replacing the Viterbi decoder with a max-log-map decoder capable of soft metric output. As a result of computer simulation in AWGN channel, there is an Eb/No performance gain of about more than 0.7~0.8dB compared to the conventional method.