• KSCI Review
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• v.15 no.1
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• pp.173-177
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• 2007

3D 디스플레이 기술이 발전함에 따라 스테레오 영상의 전송시 요구되는 비트레이트의 감소가 절실히 필요하다. 하지만, 스테레오 영상은 서로 다른 카메라에 의해 취득되기 때문에 잠재적으로 서로 차이가 있고, 이것은 디스패리티 추정시 큰 오차를 유발할 수 있으며 전송될 비트레이트에 영향을 줄 수 있다. 따라서 스테레오 영상들 사이의 밸런싱이 필요하다. 스테레오 영상의 밸런싱을 위해, 본 논문에서는 히스토그램 Specification 방법과 타깃 영상의 국부정보, 스테레오 영상간의 오차 분포를 이용한다. 히스토그램 Specification 방법은 그레이레벨의 맵핑관계를 정의한다. 따라서 이를 통해 맵핑될 레벨의 맵핑 구간을 구할 수 있다. 그 구간에서, 맵핑될 기준영상의 히스토그램 분포와 스테레오 오차값의 분포는 서로 모양이 유사할 것이다. 그러나, 폐색된 영역이나 노이즈에 의해 그 모양이 변하므로 우리는 맵핑될 픽셀들을 오차영상에서 그 픽셀들의 근방에서 구한 평균들과 오른쪽 영상(타깃 영상)에서 맵핑될 픽셀의 근방에서 구한 평균이 최소 값을 갖는 위치 값으로 맵핑한다. 제안된 방법은 실험에서 기존 방법보다 향상된 결과를 나타내는 것을 보여 준다.

• Journal of Broadcast Engineering
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• v.16 no.4
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• pp.635-646
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• 2011

In distributed video coding, low complexity encoder can be realized by shifting encoder-side complex processes to decoder-side. However, not only motion estimation/compensation processes but also complex LDPC decoding process are imposed to the Wyner-Ziv decoder, therefore decoder-side complexity has been one important issue to improve. LDPC decoding process consists of numerous iterative decoding processes, therefore complexity increases as the number of iteration increases. This iterative LDPC decoding process accounts for more than 60% of whole WZ decoding complexity, therefore it can be said to be a main target for complexity reduction. Previously, HDA (Hard Decision Aided) method is introduced for fast LDPC decoding process. For currently received parity bits, HDA method certainly reduces the complexity of decoding process, however, LDPC decoding process is still performed even with insufficient amount of parity request which cannot lead to successful LDPC decoding. Therefore, we can further reduce complexity by avoiding the decoding process for insufficient parity bits. In this paper, therefore, a parity request estimation method is proposed using bit plane-wise correlation and temporal correlation. Joint usage of HDA method and the proposed method achieves about 72% of complexity reduction in LDPC decoding process, while rate distortion performance is degraded only by -0.0275 dB in BDPSNR.

• Proceedings of the Korean Society of Broadcast Engineers Conference
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• 2010.11a
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• pp.239-241
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• 2010

분산 비디오 기술의 대표적인 기술 중 하나는 와이너 지브 부호화 기술이다. 와이너 지브 부호화 구조에서 보조정보는 인트라 복호화된 키 픽처들을 이용하여 생성한다. 키 픽처의 객관적 화질은 보조정보의 성능에 많은 영향을 끼치고, 잡음이 많은 보조정보를 복호화에 이용할 경우 부호화로부터 많은 패리티 비트를 요구하게 되어 율 왜곡 성능을 저하된다. 기존의 부호화 기술은 키 픽처 부호화 시 Quantization Matrix에 따라 미리 정의된 양자화 계수를 이용한다. 본 논문에서는 미리 정의된 양자화 계수 보다 낮은 계수 값을 사용하여 부호화 하는 방법을 제안한다. 제안방법은 키 픽처의 객관적 화질이 높아짐에 따라 보조정보의 화질을 향상시킨다. 잡음이 적은 보조정보는 와이너 지브 복호화 시 율 왜곡 성능을 향상시킨다. 실험결과는 기존 방법에 비해 최대 0.7dB에 이르는 성능향상을 보인다.

• The Journal of Korean Institute of Communications and Information Sciences
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• v.36 no.8C
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• pp.522-528
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• 2011

The iterative detection and decoding (IDD) has been shown to dramatically improve the bit error rate (BER) performance of the multiple-input multiple-output (MIMO) communication systems. However, these techniques require a high computational complexity since it is required to compute the soft decisions for each bit. In this paper, we show IDD comprised of sphere decoder with low-density parity check (LDPC) codes and present the tree search strategy, called a layer symbol search (LSS), to obtain soft decisions with a low computational complexity. In addition, an adaptive early termination is proposed to reduce the computational complexity during an iteration between an inner sphere decoder and an outer LDPC decoder. It is shown that the proposed approach can achieve the performance similar to an existing algorithm with 70% lower computational complexity compared to the conventional algorithms.

• Journal of the Institute of Convergence Signal Processing
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• v.11 no.3
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• pp.244-249
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• 2010

The design of error correction code with low complexity has a good attraction for next generation multi-level cell flash memory. Sharing sub-expressions is effective method to reduce complexity and chip size. This paper proposes a new design method of m-bit parallel BCH encoder based on serial linear feedback shift register structure with low complexity using sub-expression. In addition, general algorithm for obtaining the sub-expression is introduced. The sub-expression can be expressed by matrix operation between sub-matrix of generator matrix and sum of two different variables. The number of the sub-expression is restricted by. The obtained sub-expressions can be shared for implementation of different m-parallel BCH encoder. This paper is not focused on solving a problem (delay) induced by numerous fan-out, but complexity reduction, expecially the number of gates.

• The Journal of Korean Institute of Communications and Information Sciences
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• v.32 no.9C
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• pp.801-809
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• 2007

LDPC Low Density Parity Check) code, which is an error correcting code determined to be applied to the 4th generation mobile communication systems, requires a heavy computational complexity due to iterative decodings to achieve a high BER performance. This paper proposes an algorithm to reduce the number of decoding iterations to increase performance of the decoder in decoding latency and power consumption. Measuring changes between the current decoded LLR values and previous ones, the proposed algorithm predicts directions of the value changes. Based on the prediction, the algorithm inverts the sign bits of the LLR values to speed up convergence, which means parity check equation is satisfied. Simulation results show that the number of iterations has been reduced by about 33% without BER performance degradation in the proposed decoder, and the power consumption has also been decreased in proportional to the amount of the reduced decoding iterations.

• The Journal of Korean Institute of Communications and Information Sciences
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• v.38A no.9
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• pp.750-758
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• 2013

In this paper, we introduce the low-density parity-check (LDPC) coded orthogonal frequency division multiplexing (OFDM) subframe reordering scheme for achieving equal combined power allocation in type I hybrid automatic repeat request (H-ARQ) systems and analyze the performance improvement by using the channel capacity. Also, it is confirmed that the layered decoding for subframe reordering scheme in H-ARQ systems gives faster convergence speed. It is verified from numerical analysis that a subframe reordering pattern having larger channel capacity shows better bit error rate (BER) performance. Therefore the subframe reordering pattern achieving equal combined power allocation for each subframe maximizes the channel capacity and outperforms other subframe reordering patterns. Also, it is shown that the subframe reordering scheme for achieving equal combined power allocation gives better performance than the conventional Chase combining scheme without increasing the decoding complexity.

• Journal of the Korea Institute of Information and Communication Engineering
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• v.14 no.12
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• pp.2783-2790
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• 2010

In this paper, we first review LDPC codes in general and a belief propagation algorithm that works in logarithm domain. LDPC codes, which is chosen 802.11n for wireless local access network(WLAN) standard, require a large number of computation due to large size of coded block and iteration. Therefore, we presented three kinds of low computational algorithms for LDPC codes. First, sequential decoding with partial group is proposed. It has the same H/W complexity, and fewer number of iterations are required with the same performance in comparison with conventional decoder algorithm. Secondly, we have apply early stop algorithm. This method reduces number of unnecessary iterations. Third, early detection method for reducing the computational complexity is proposed. Using a confidence criterion, some bit nodes and check node edges are detected early on during decoding. Through the simulation, we knew that the iteration number are reduced by half using subset algorithm and early stop algorithm is reduced more than one iteration and computational complexity of early detected method is about 30% offs in case of check node update, 94% offs in case of check node update compared to conventional scheme. The LDPC decoder have been implemented in Xilinx System Generator and targeted to a Xilinx Virtx5-xc5vlx155t FPGA. When three algorithms are used, amount of device is about 45% off and the decoding speed is about two times faster than convectional scheme.