• Proceedings of the Korean Society for Noise and Vibration Engineering Conference
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• 2006.05a
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• pp.326-331
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• 2006

The durability of recent motors is longer than the past one because there are the rapid technique development of the automobile industry and the vehicle maintenance of users. And then the importance of the durability test due to vibration is increased from day to day. So full vehicle and parts companies accomplish the durability test using various methods. The most public test method among them is the reliable field test but it bring on higher cost and period of the development process. The durability test using MAST(multi axis simulation table) is a solution in order to improve the development process of automobiles. Generally its excitation source uses the optimized road profiles that are obtained by the road test of belgian road, country road, cobbleston road and so on instead of a real field but the interrelations and influences accordingly vehicle damage are considered by a field test between specific roads and real fields in the first place. Therefore this study, in order to accomplish a basic research for the durability test using the MAST, performed on the real field driving test at various domestic roads and the results which are analyzed by PSD(power spectrum density) are compared with relative sensitivity among the roads. Consequently they can present a basic material for generation of road profiles which is applied to the durability test using MAST.

• Journal of the Korea Academia-Industrial cooperation Society
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• v.17 no.9
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• pp.21-26
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• 2016

This paper presents a step-down DC-DC buck converter with a CCM/DCM dual-mode function for the internal power stage of portable electronic device. The proposed converter that is operated with a high frequency of 1 MHz consists of a power stage and a control block. The power stage has a power MOS transistor, inductor, capacitor, and feedback resistors for the control loop. The control part has a pulse width modulation (PWM) block, error amplifier, ramp generator, and oscillator. In this paper, an external capacitor for compensation has been replaced with a multiplier equivalent CMOS circuit for area reduction of integrated circuits. In addition, the circuit includes protection block, such as over voltage protection (OVP), under voltage lock out (UVLO), and thermal shutdown (TSD) block. The proposed circuit was designed and verified using a $0.18{\mu}m$ CMOS process parameter by Cadence Spectra circuit design program. The SPICE simulation results showed a peak efficiency of 94.8 %, a ripple voltage of 3.29 mV ripple, and a 1.8 V output voltage with supply voltages ranging from 2.7 to 3.3 V.