• Title/Summary/Keyword: 트랜치

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Lateral Structure Transistor by Silicon Direct Bonding Technology (실리콘 직접접합 기술을 이용한 횡방향 구조 트랜지스터)

  • 이정환;서희돈
    • Proceedings of the Korean Institute of Electrical and Electronic Material Engineers Conference
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    • pp.759-762
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    • 2000
  • Present transistors which have vertical structure show increased parasitic capacitance characteristics in accordance with the increase of non-active base area and collector area, consequently have disadvantage for high speed switching performance. In this paper, a horizontal structure transistor which has minimized parasitic capacitance in virtue of SDB(Silicon Direct Bonding) wafer and oxide sidewall isolation utilizing silicon trench technology is presented. Its structural characteristics were designed by ATHENA(SUPREM4), the process simulator from SILVACO International, and its performance was proven by ATLAS, the device simulator from SILVACO International. The performance of the proposed horizontal structure transistor was certified through the VCE-lC characteristics curve, $h_{FE}$ -IC characteristics, and GP-plot.

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Unified Model for Alpha-particle-induced Charge Collection (알파 입자에 의한 전하 수집량에 대한 통합 모델)

  • Shin, Hyung-Soon
    • Journal of the Korean Institute of Telematics and Electronics D
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    • v.36D no.1
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    • pp.83-89
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    • 1999
  • A Unified model for the alpha-particle-induced charge collection has been developed. By accounting for funneling and diffusion charges separately, new model accurately describes the dependence of collected charge on junction size, junction bias, injection energy, injection angle, injection point, and trench oxide depth.

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A New Vertical Channel LDMOS(lateral double diffused MOSFEET) (수직 방향 채널 LDMOS(lateral double diffused MOSFEET))

  • Lee, Seung-Chul;Oh, Jae-Geun;Han, Min-Koo;Choi, Yearn-Ik
    • Proceedings of the KIEE Conference
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    • pp.1424-1426
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    • 2001
  • 본 논문에서는 채널과 드리프트 영역을 트랜치 안쪽에 형성하여 소자 크기를 줄임으로서 항복전압을 감소시키지 않고 낮은 온 저항을 얻을 수 있는 새로운 수직방향 채널 LDMOS(Lateral Double Diffused MOSFET)를 제안한다. 기존의 LDMOS 구조와 비교 할 때 동일한 60V의 항복 전압에서 소자 크기가 4${\mu}m$로 줄어들었고 이에 따라 온 저항은 절반의 수준으로 (0.45 m${\Omega}cm^2$) 감소하였다. 또한 소자 크기의 감소로 인해 전력용 집적회로를 구성할 때 집적도가 두 배 가량 증가하게 된다.

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A New Structure of SOI MOSFETs Using Trench Mrthod (트랜치 기법을 이용한 SOI MOSFET의 전기적인 특성에 관한 연구)

  • Park, Yun-Sik;Sung, Man-Young;Kang, Ey-Goo
    • 한국컴퓨터산업교육학회:학술대회논문집
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    • pp.67-70
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    • 2003
  • In this paper, propose a new structure of MOFET(Metal-Oxide-Semiconductor Field Effect Transistor) which is widely application for semiconductor technologies. Eleminate the latch-up effect caused by closed devices when conpose a electronic circuit using proposed devices. In this device have a completely isolation structure, and advantage of leakage current elimination. Each independent devices are isolated by trench-well and oxide layer of SOI substrate. Using trench gate and self aligned techniques reduces parasitic capacitance between gate and source, drain. In this paper, we proposed the new structure of SOI MOSFET which has completely isolation and contains trench gate electrodes and SOI wafers. It is simulated by MEDICI that is device simulator.

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The Change of Electrical Characteristics in the EST with Trench Electrodes (트랜치 전극을 가진 Emitter Switched Thyristor의 전기적 특성 변화)

  • Kim, Dae-Won;Kim, Dae-Jong;Sung, Man-Young;Kang, Ey-Goo;Lee, Dong-Hee
    • 한국컴퓨터산업교육학회:학술대회논문집
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    • pp.71-74
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    • 2003
  • A vertical trench electrode type EST has been proposed in this paper. The proposed device considerably improve the snap-back effect which leads to a lot of problem of device applications. In this paper, the vertical dual gate Emitter Switched Thyristor(EST) with trench electrode has been proposed for improving snap-back effect. It is observed that the forward blocking voltage of the proposed device is 800V. The conventional EST of the same size were no more than 633V. Because the proposed device was constructed of trench-type electrode, the electric field moved toward trench-oxide layer, and the punch through breakdown of the proposed EST is occurred at latest.

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A Study on the Design and Electrical Characteristics of High Performance Smart Power Device (고성능 Smart Power 소자 설계 및 전기적 특성에 관한 연구)

  • Ku, Yong-Seo
    • Journal of IKEEE
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    • v.7 no.1
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    • pp.1-8
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    • 2003
  • In this study, the high performance BCD device structure which satisfies the high voltage and fast switching speed characteristics is devised. Through the process and device simulation, optimal process spec. & device spec. are designed. We adapt double buried layer structure, trench isolation process, n-/p-drift region formation and shallow junction technology to optimize an electrical property as mentioned above. This I.C consists of 20V level high voltage bipolar npn/pnp device, 60V level LDMOS device, a few Ampere level VDMOS, 20V level CMOS device and 5V level logic CMOS.

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A Study On MOSFET Hump Characteristics with STI Structures (STI 구조에서 발생하는 MOSFET Hump 특성에 관한 연구)

  • 이용희;정상범;이천희
    • Proceedings of the Korean Information Science Society Conference
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    • pp.674-676
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    • 1998
  • 소자가 sub-quarter um급으로 축소됨에 따라 STI(Shallow Trench Isolation) 기술은 고 집적도의 ULSI 구현에 있어서 중요한 격리 방법으로 많이 사용되고 있다. 현재의 STI 기술은 주로 실리콘 기판을 식각 후 절연물질로 빈 공백이 없이 채우는 (void-free gap filling) 방법 [1,2]과 절연물질을 다시 표면 근처까지 CMP(Chemical Mechnical Polishing)로 etchback하여 평탄화를 하는 방법이 주요한 기술이 되고 있다. 또한 STI 구조로된 격리구조에서 만들어진 MOSFET의 전기적인 특성은 트랜치 격리의 상부 부분의 형태와 gap-filling 물질에 따라 큰 영향을 받게된다. 따라서 본 논문에서는 STI 구조로 만들어진 격리 구조에서 MOSFET의 hump 특성에 관해 연구하였다. 그 결과 hump는 STI 모서리에서 필드 옥사이드의 recess에 의한 모서리 부분에서의 전계 집중과 boron의 segration에 기인한 농도 감소로 인해 hump가 발생하는 것으로 나타났다.

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The Fabrication of Micro-heaters with Low Consumption Power Using SOI and Trench Structures and Its Characteristics (SOI와 트랜치 구조를 이용한 초저소비전력형 미세발열체의 제작과 그 특성)

  • 정귀상;홍석우;이원재;송재성
    • Journal of the Korean Institute of Electrical and Electronic Material Engineers
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    • v.14 no.3
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    • pp.228-233
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    • 2001
  • This paper presents the optimized design, fabrication and thermal characteristics of micro-heaters for thermal MEMS (micro elelctro mechanical system) applications usign SOI (Si-on-insulator) and trench structures. The micro-heater is based on a thermal measurement principle and contains for thermal isolation regions a 10㎛ thick Si membrane with oxide-filled trenches in the SOI membrane rim. The micro-heater was fabricated with Pt-RTD (resistance thermometer device) on the same substrate by suing MgO as medium layer. The thermal characteristics of the micro-heater wit the SOI membrane is 280$\^{C}$ at input power 0.9W; for the SOI membrane with 10 trenches, it is 580$\^{C}$ due to reduction of the external thermal loss. Therefore, the micro-heater with trenches in SOI membrane rim provides a powerful and versatile alternative technology for improving the performance of micro-thermal sensors and actuators.

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Analysis of Electrical Characteristics of High-Density Trench Gate Power DMOSFET Utilizing Self-Align and Hydrogen Annealing Techniques (자기 정열과 수소 어닐링 기술을 이용한 고밀도 트랜치 게이트 전력 DMOSFET의 전기적 특성 분석)

  • 박훈수;김종대;김상기;이영기
    • Journal of the Korean Institute of Electrical and Electronic Material Engineers
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    • v.16 no.10
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    • pp.853-858
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    • 2003
  • In this study, a new simplified technology for fabricating high density trench gate DMOSFETs using only three mask layers and TEOS/nitride spacer is proposed. Due to the reduced masking steps and self-aligned process, this technique can afford to fabricate DMOSFETs with high cell density up to 100 Mcell/inch$^2$ and cost-effective production. The resulting unit cell pitch was 2.3∼2.4${\mu}$m. The fabricated device exhibited a excellent specific on-resistance characteristic of 0.36m$\Omega$. cm$^2$ with a breakdown voltage of 42V. Moreover, time to breakdown of gate oxide was remarkably increased by the hydrogen annealing after trench etching.

The Research of Deep Junction Field Ring using Trench Etch Process for Power Device Edge Termination

  • Kim, Yo-Han;Kang, Ey-Goo;Sung, Man-Young
    • Journal of IKEEE
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    • v.11 no.4
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    • pp.235-238
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    • 2007
  • The planar edge termination techniques of field-ring and deep junction field-ring were investigated and optimized using a two-dimensional device simulator TMA MEDICI. By trenching the field ring site which would be implanted, a better blocking capability can be obtained. The results show that the p-n junction with deep junction field-ring can accomplish near 30% increase of breakdown voltage in comparison with the conventional field-rings. The deep junctionfield-rings are easy to design and fabricate and consume same area but they are relatively sensitive to surface charge. Extensive device simulations as well as qualitative analyses confirm these conclusions.

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