• Proceedings of the Korea Information Processing Society Conference
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• 2010.11a
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• pp.973-974
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• 2010

본 논문에서는 XFP(10 Gb/s Small Form Factor Pluggable) 트랜시버 모듈의 정확한 데이터 전송을 위해 저전력 FEC를 설계하였다. 현재 많이 사용되며 버스트 에러에 강한 Reed-solomon코드를 구현하고 코드의 분산 연산을 통해 저전력 RS코드를 구현하였다. 본 논문에서 제안한 코드는 기존의 RS코드 대비 20% 면적이 감소하는 것을 확인할 수 있었으며, 또한 전력소모가 10% 감소되는 것을 확인 할 수 있었다.

• Proceedings of the Korea Information Processing Society Conference
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• 2010.11a
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• pp.1057-1058
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• 2010

본 논문에서는 SFP+ 트랜시버 모듈의 저전력 데이터 전송을 위해 전송 알고리듬인 5B6B의 병렬연산 알고리듬을 설계하였다. SFP+의 기본 전송 알고리듬인 5B6B는 소형화된 SFP+의 전력소모를 줄이기 위해 제안하였으며, 본 논문에서 제안한 코드는 종래의 전송 알고리듬 대비 전력소모가 10% 감소되는 것을 확인 할 수 있었다.

• Proceedings of the Optical Society of Korea Conference
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• 2002.11a
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• pp.186-187
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• 2002

• Journal of the Institute of Electronics Engineers of Korea SD
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• v.41 no.2
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• pp.1-8
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• 2004

This paper describes the design of monolithic optical transceiver circuitry being used as a part of the fiber optic modules. It has been designed in 0.6 ${\mu}{\textrm}{m}$ 2-poly 3 metal silicon CMOS analog technology and operates at 155.52 Mbps(STM-1) data rates. It drives laser diode to transmit intensity modulated optical signal according to 155.52 Mbps electrical data from system. Also, it receives 155.52 Mbps optical data that transmitted from other systems and converts it to electrical data using photo diode and amplifier. To avoid noise and interference between transmitter and receiver on one chip, layout techniques such as special placement, power supply separation, guard ring, and protection wall were used in the design. The die area is 4 ${\times}$ 4 $\textrm{mm}^2$ and the estimated power dissipation is less than 900 ㎽ with a single 5 V supply.

• Journal of the Institute of Electronics Engineers of Korea SD
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• v.41 no.9
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• pp.11-17
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• 2004

This paper describes the implementation of monolithic optical transceiver circuitry being used as a part of the fiber optic modules. It has been fabricated in 0.6 ${\mu}{\textrm}{m}$ 2-poly 3-metal silicon CMOS analog technology and operates at 155.52 Mbps(STM-1) data rates. It drives laser diode to transmit intensity modulated optical signal according to 155.52 Mbps electrical data from system. Also, it receives 155.52 Mbps optical data that transmitted from other systems and converts it to electrical data using photo diode and amplifier. To avoid noise and interference between transmitter and receiver on one chip, layout techniques such as special placement, power supply separation, guard ring, and protection wall were used in the design. The die area is 4 ${\times}$ 4 $\textrm{mm}^2$, and it has 32.3 ps rms and 335.9 ps peak to peak jitter on loopback testing. the measured power dissipation of whole chip is 1.15 W(230 mW) with a single 5 V supply.

• Journal of the Institute of Electronics Engineers of Korea TC
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• v.43 no.10 s.352
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• pp.46-54
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• 2006

In this paper, we propose a digital transceiver that can overcome the problems which current analog transceivers have. For the proposed transceiver, we assumed a frequency resource that consists of discrete and narrow channels. We also assumed that person-to-group, group-to-group, as well as person-to-person, voice and data communications with moderate security should be devisedand the data rate is 1 Mbps with simultaneous voice and data. Frequency hewing spread spectrum (FH-SS) and differential 8-PSK (D8PSK) were adopted for security reasons and bandwidth constraints, and for the reduction of implementation complexity, respectively. For the carrier and the symbol timing recovery, the structure of the preamble was proposed based on the IEEE 802.11 FHSS frame format to improve detection probability. The computer simulation results and power budget analysis implies that the proposed system can be usedin simple wireless communications in place of such as analog walkie-talkies.

• Journal of the Institute of Electronics Engineers of Korea SD
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• v.44 no.1
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• pp.68-75
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• 2007

A single chip NFC transceiver supporting not only NFC active and passive mode but also 13.56MHz RFID reader and tag mode was designed and fabricated. The proposed NFC transceiver can operate as a RFID tag even without external power supply which has dual antenna structure for initiator and target. The area increment due to additional target antenna is negligible because the target antenna is constructed by using a shielding layer of initiator antenna. The analog front end circuit of the proposed NFC transceiver consists of a transmitter and receiver of reader/writer block supporting NFC initiator or RFID reader mode, and a tag circuit for target of passive NFC mode or RFID tag mode. The maximum baud rate of the proposed NFC device is 212kbps by using UART serial interface. The chip has been designed and fabricated using a Magnachip's $0.35{\mu}m$ double poly 4-metal CMOS process, and the effective area of the chip is 2200um by 3600um.

• Journal of the Institute of Electronics and Information Engineers
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• v.51 no.4
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• pp.49-58
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• 2014

A low-swing differential near-ground signaling (NGS) transceiver for low-power high-speed mobile I/O interface is presented. The proposed transmitter adopts an on-chip regulated programmable-swing voltage-mode driver and a pre-driver with asymmetric rising/falling time. The proposed receiver utilizes a new multiple gain-path differential amplifier with feed-forward capacitors that boost high-frequency gain. Also, the receiver incorporates a new adaptive bias generator to compensate the input common-mode variation due to the variable output swing of the transmitter and to minimize the current mismatch of the receiver's input stage amplifier. The use of the new simple and effective impedance matching techniques applied in the transmitter and receiver results in good signal integrity and high power efficiency. The proposed transceiver designed in a 65-nm CMOS technology achieves a data rate of 13 Gbps/channel and 0.3 pJ/bit (= 0.3 mW/Gbps) high power efficiency over a 10 cm FR4 printed circuit board.

• Journal of the Institute of Electronics Engineers of Korea CI
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• v.41 no.4
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• pp.41-49
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• 2004

In this paper, a design and measurement method for FPGA embedded gigabit-transceiver is presented. Altera's Stratix GX device which is general purpose transceiver called GXB was used for implementing PCI Express transceiver. PCI Express is the generation high performance serial I/O bus used to interconnect peripheral devices. After GXB was set follow by PCI Express specifications, the design has been verified by timing simulation and implemented as hardware. We tested it as follow. First GXB internal digital and analog block test second GXB transmitter signal integrity test called Eye mask test, third GXB high-speed serial I/O buffer and on-chip termination test and the last GXB protocol test. This paper shows all the design and measurement procedure about FPGA embedded gigabit-transceiver.

• Journal of the Institute of Electronics and Information Engineers
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• v.49 no.11
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• pp.24-35
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• 2012

In this paper, we propose a dynamic lane control scheme with a traffic predictor module and a rate controller for reconciling with commercial optical PHY modules in energy efficient optical Ethernet systems. The commercial high speed optical Ethernet system capable of 40/100Gbps employs 4 or 10 multiple optical transceivers over WDM or multiple optical links. Each of the transceivers is always turned on even if the link is idle. To save energy, we propose the dynamic lane control scheme. It allows that several links may be entirely turned off in a low traffic load and frames are handled on the remaining active links. To preserve the byte order even if the number of active links may be changed, we propose a rate controller to be sat on the reconciliation sublayer. The main role of the controller is to insert null byte streams into the xGMII of inactive lanes. For the PHY module, the null input streams corresponding to inactive lanes will be disregarded on inactive PMDs. It is very handy to implement the rate controller module with MAC in FPGA without any modification of commercial PHYs. It is very crucial to determine the number of active links based on the fluctuated traffic load, we provide a simple traffic predictor based on both the current transmission buffer size and the past one with different weighting factors for adapting to the traffic load fluctuation. Using the OMNET++ simulation framework, we provide several performance results in terms of the energy consumption.