• Journal of the Institute of Electronics Engineers of Korea SD
• /
• v.38 no.3
• /
• pp.211-219
• /
• 2001

This paper describes a read-only CMOS transponder IC for RFID applications. A full-wave rectifier implemented using NMOS transistors supplies the transponder with a dc supply voltage using the magnetic field generated from a reader. A 64-bit ROM has been designed for a data memory. Front-end impedance modulation and Manchester coding are used for transmitting the data from the transponder memory to the reader. A new damping circuit which has almost constant damping rate under the variations of the distance between the transponder and the reader has been employed for impedance modulation. The designed circuit has been fabricated using a 0.65${\mu}{\textrm}{m}$2-poly, 2-metal CMOS process. Die area is 0.9mm$\times$0.4mm. Measurement results show that it has a constant damping rate of around 20~25% and a data transmission rate of 3.9kbps at a 125KHz RF carrier. The power required for reading operation is about 100㎼. The measured reading distance is around 7cm.

• The KIPS Transactions:PartB
• /
• v.12B no.6 s.102
• /
• pp.637-646
• /
• 2005

Most of the multimedia contents for DBM services art provided as MPEG-2 bit streams. However, they have to be transcoded to H.264 bit streams for practical services because the standard video codec for DMB is H.264. The existing transcoder architecture is Cascaded Pixel-Domain Transcoding Architecture, which consists of the MPEG-2 dacoding phase and the H.264 encoding phase. This architecture can be easily implemented using MPEG-2 decoder and H.264 encoder without source modifying. However. It has disadvantages in transcoding time and DCT-mismatch problem. In this paper, we propose two kinds of transcoder architecture, DCT-OPEN and DCT-CLOSED, to complement the CPDT architecture. Although DCT-OPEN has lower PSNR than CPDT due to drift problem, it is efficient for real-time transcoding. On the contrary, the DCT-CLOSED architecture has the advantage of PSNR over CPDT at the cost of transcoding time.

• Journal of the Korea Institute of Information and Communication Engineering
• /
• v.22 no.7
• /
• pp.993-1000
• /
• 2018

This paper proposes a low-dropout voltage regulator(LDO) using self-cascode structure. The self-cascode structure was optimized by adjusting the channel length of the source-side MOSFET and applying a forward voltage to the body of the drain-side MOSFET. The self-cascode of the input differential stage of the error amplifier is optimized to give higher transconductance, but the self-cascode of the output stage is optimized to give higher output resistance, The proposed LDO using self-cascode structure was designed by a $0.18{\mu}m$ CMOS technology and simulated using SPECTRE. The load regulation of the proposed LDO regulator was 0.03V/A, whereas that of the conventional LDO was 0.29V/A. The line regulation of the proposed LDO regulator was 2.23mV/V, which is approximately three times improvement compared to that of the conventional LDO. The transient response of the proposed LDO regulator was 625ns, which is 346ns faster than that of the conventional LDO.

• Journal of the Korea Computer Industry Society
• /
• v.2 no.10
• /
• pp.1253-1260
• /
• 2001

In this paper, a new voltage-controlled tunable analog active element for low-voltage applications and information protection is proposed. The proposed active element is composed of the CMOS complementary cascode circuit which can extend transconductance of an element. Therefore, the unity gain frequency which is determined transconductance is increased than that of the conventional element. And then these results are verified by the $0.25\mutextrm{m}$ CMOS n-well parameter HSPICE simulation. As a result, the gain and the unity gain frequency are 42㏈ and 200MHz respectively in the element on 2V supply voltage. And power dissipation of the designed circuit is 0.32mW.

• Journal of the Institute of Electronics Engineers of Korea CI
• /
• v.43 no.4 s.310
• /
• pp.113-122
• /
• 2006

In this paper, we propose a fuzzy method to control bit-rate in the DCT Domain. The method consists of a bit-rate allocation with fuzzy measures and a least-distortion bit-rate reduction. Fuzzy measures are calculated by the code length, the discontinuity ambiguity, and the neighborhood momentum in each DCT block. These measures are summed with weights and form a reduction fuzziness to indicate the degree of preferable reduction. Using the reduction fuzziness. each DCT block is filtered by the least-distortion reduction method to adjust the bit-rate for the target bandwidth. In the experiment, we show the results that the transcoded video quality by the method is better and the bandwidth is more regular than those of existing methods in both visually and quantitatively.

• Journal of Korea Multimedia Society
• /
• v.6 no.2
• /
• pp.319-324
• /
• 2003

In this paper, a new wideband tunable analog element for multimedia system is proposed. The proposed active element is composed of the complementary cascode circuit which can extend transconductance of an element. Therefore, the unity gain frequency which is determined transconductance is increased than that of the conventional element. And then these results are verified by the 0.22$\mu\textrm{m}$ CMOS n-well parameter simulation. As a result, the gam and the unity gam frequency are 42dB and 200MHz on 2V supply voltage. And power dissipation of the designed element is 0.32mW.

• Journal of the Korean Society for Aeronautical & Space Sciences
• /
• v.31 no.10
• /
• pp.89-96
• /
• 2003

In this paper, a CCSDS(Consultative Committee for Space Data Systems) telecommand(TC) decryptor for the security of geostationary communications satellite was implemented. For the confidentiality of CCSDS TC datalink security, Option-A which implements the security services below the transfer sublayer was selected. Also CFB(Cipher Feedback) operation mode of DES(Data Encryption Standard) was used for the encryption of 56-bit data bits in 64-bit codeblock. To verify Decryptor function, the DES CFB logic implemented on A54SX32 FPGA(Field Programmable Gate Array) was integrated with interface and control logics in a PCB(Printed Circuit Board). Using a function test PC, the encrypted codeblocks were generated, transferred into the decryptor, decrypted, and the decrypted codeblocks were transmitted to the function test PC, and then compared with the source codeblocks. Through LED(Light Emitting Diode) ON operation by driving the relay related to Op-code decoded and the comparison between the codeblock output waveforms measured and those simulated, the telecommand decryptor function was verified.

• Journal of KIISE:Software and Applications
• /
• v.37 no.5
• /
• pp.403-410
• /
• 2010

Monad in Haskell allows one to do imperative-style programming as well as pure functional programming. In this work, we characterize monadic abstraction and its programming technique by restructuring an assembly language interpreter coded in pure functional style into the one by the monadic style. Monad programming consists of two phases; the State monad is applied to a stack and a symbol table, and then a State Monad Transformer integrating these two monads is constructed. As a result, we can see that the program code by monad programming is much clearer and more intuitive than one written in the pure functional style.

• Proceedings of the IEEK Conference
• /
• 2000.09a
• /
• pp.983-986
• /
• 2000

본 논문에서는 저전압(2V) 동작이 가능하도록 완전차동 구조의 아날로그 능동소자에 전압조절을 위한 튜닝 회로를 추가한 능동소자를 제안하였다. 아날로그 능동소자는 이득특성에 영향을 주는 트랜스컨덕턴스값을 증가시키기 위해 CMOS 상보형 캐스코드 방식을 이용하여 구성되었다. 0.25㎛ CMOS n-well 공정 파라미터를 이용한 HSPICE 시뮬레이션 결과, 제안된 아날로그 능동소자는 비우성극점의 제거로 안정성이 향상되었으며, 2V 공급전압하에서 42dB의 이득값과 200MHz의 단위 이득주파수 특성을 나타내었다. 소비전력값은 0.32mW를 나타내었다.

• The Journal of Korean Institute of Communications and Information Sciences
• /
• v.26 no.5B
• /
• pp.639-644
• /
• 2001

본 논문에서는 저전압(2V) 동작이 가능하도록 high-swing cascode 방식을 이용한 능동소자를 제안하고, 이를 이용하여 400MHz의 차단주파수 특성을 나타내는 저역통과 능동필터를 설계하였다. 제안된 적분기는 이득특성에 영향을 주는 트랜스컨덕스값을 증가시키기 위해 CMOS 상보형 캐스코드 방식을 이용하여 구성되었다. 0.25$\mu\textrm{m}$ CMOS n-well 공정 파라미터를 이용한 Hspice 시뮬레이션 결과, 제안된 적분기는 2V 공급전압하에서 42dB의 이득값과 200MHz의 단위이득주파수 특성을 나타내었다. 또한 이를 이용하여 설계된 저역통과 능동필터는 400MHz의 차단주파수 특성을 나타내고 368MHz에서 416MHz까지 튜닝이 가능하였다.