• Journal of the Korean Society for Aeronautical & Space Sciences
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• v.41 no.10
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• pp.805-812
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• 2013

The operational flight program(OFP) which has the functions of I/O processing with avionics, flight control logic calculation, fault diagnosis and redundancy mode is embedded in the flight control computer of Smart UAV. The OFP was developed in the environment of PowerPC 755 processor and VxWorks 5.5 real-time operating system. The OFP consists of memory access module, device I/O signal processing module and flight control logic module, and each module was designed to hierarchical structure. Memory access and signal processing modules were verified from bench test, and flight control logic module was verified from hardware-in-the-loop simulation(HILS) test, ground integration test, tethered test and flight test. This paper describes development environment, software structure, verification and management method of the OFP.

• The Transactions of the Korea Information Processing Society
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• v.5 no.5
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• pp.1333-1344
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• 1998

In comparison to traditional monolithic kernel, the microkernel based operating system has slower speed. But Microkernel based OS suites for multi-computer system, because It has benefits in the modularity and portability point of view. Each unit and memory of a processor must be initialized by using the boot information so that the multi-computer system OS can actively run the function of the system. This paper describes the microkernel initialization of OSF/1 AD3 MISIX that is based on OSF/1 AD3 for SPAX. It will introduce the initialization of microkernel for the SPAX which is High-speed Parallel Processing system in terms of Boot, Initialization related hardware and memory address space construction. This paper will also state the test result based on test environments. Microkernel tested in single node system that has 4 processors.

• Journal of KIISE
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• v.43 no.9
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• pp.947-952
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• 2016

Most data centers attempt to consolidate servers using virtualization technology to efficiently utilize limited physical resources. Moreover, virtualized systems have commonly adopted contents-based page sharing mechanism for page deduplication among virtual machines (VMs). However, previous page sharing schemes are limited by the inability to effectively manage accumulated hints which mean sharable pages in stack. In this paper, we propose a priority-based hint management scheme to efficiently manage accumulated hints, which are sent from guest to host for improving page sharing opportunity in virtualized systems. Experimental results show that our scheme removes pages with low sharing potential, as compared with the previous schemes, by efficiently managing the accumulated pages.

• Journal of Aerospace System Engineering
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• v.12 no.5
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• pp.48-53
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• 2018

In this study, Real-Time Operating System(RTOS) and 3-D collision avoidance algorithm are implemented to three different Miciro Controller Unit(MCU)s and their performances compared. We selected Microchip Technology's ATmega2560, STM's ARM Cortex-M3 and ARM Cortex-M4, because they are widely used. FreeRTOS, an open-source operating system, was also used. The 3D collision avoidance algorithm consists of the vertical and the horizontal avoidance algorithm, which is implemented using C++. The performances of the MCUs were compared with respect to used memory and calculation time. As a result, Cortex-M4's calculation time was the fastest and ATmega2560 used least memory.

• Journal of IKEEE
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• v.24 no.1
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• pp.200-207
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• 2020

In this paper, an area-efficient feature extractor was proposed for security surveillance radar systems and FPGA-based implementation results were presented. In order to reduce the memory requirements, features extracted from Doppler profile for FFT window-size are used, while those extracted from total spectrogram for frame-size are excluded. The proposed feature extractor was design using Verilog-HDL and implemented with Xilinx Zynq-7000 FPGA device. Implementation results show that the proposed design can reduce the logic slice and memory requirements by 58.3% and 98.3%, respectively, compared with the existing research. In addition, security surveillance radar system with the proposed feature extractor was implemented and experiments to classify car, bicycle, human and kickboard were performed. It is confirmed from these experiments that the accuracy of classification is 93.4%.

• The Journal of Korean Institute of Communications and Information Sciences
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• v.34 no.4B
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• pp.403-418
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• 2009

IP version 6 (IPv6) is a new If addressing scheme that has 128-bit address space. IPv6 is proposed to solve the address space problem of IP version 4 (IPv4) which has 32-bit address space. For a given IPv6 routing set, if a forwarding table is built using a trio structure, the trio has a lot more levels than that for IPv4. Hence, for IPv6 address lookup, the binary search on trio levels would be more appropriate and give better search performance than linear search on trio levels. This paper proposes a new IPv6 address lookup algorithm performing binary search on trio levels. The proposed algorithm uses a Bloom filter in pre-filtering levels which do not have matching nodes, and hence it reduces the number of off-chip memory accesses. Simulation has been performed using actual IPv6 routing sets, and the result shows that an IPv6 address lookup can be performed with 1-3 memory accesses in average for a routing data set with 1096 prefixes.

• Journal of the Korea Institute of Information Security & Cryptology
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• v.22 no.3
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• pp.495-504
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• 2012

This paper presents various speed optimization techniques for software implementation of the HIGHT block cipher on CPUs and GPUs. We considered 32-bit and 64-bit operating systems for CPU implementations. After we applied the bit-slicing and byte-slicing techniques to HIGHT, the encryption speed recorded 1.48Gbps over the intel core i7 920 CPU with a 64-bit operating system, which is up to 2.4 times faster than the previous implementation. We also implemented HIGHT on an NVIDIA GPU equipped with CUDA, and applied various optimization techniques, such as storing most frequently used data like subkeys and the F lookup table in the shared memory; and using coalesced access when reading data from the global memory. To our knowledge, this is the first result that implements and optimizes HIGHT on a GPU. We verified that the byte-slicing technique guarantees a speed-up of more than 20%, resulting a speed which is 31 times faster than that on a CPU.

• Journal of the Korea Society of Computer and Information
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• v.27 no.9
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• pp.149-155
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• 2022

The popularity of e-commerce systems on the Internet is increasing day by day, and the recommendation system, as a core function of these systems, greatly reduces the effort to search for desired products by recommending products that customers may prefer. The collaborative filtering technique is a recommendation algorithm that has been successfully implemented in many commercial systems, but despite its popularity and usefulness in academia, the memory-based implementation has inaccuracies in its reference neighbor. To solve this problem, this study proposes a new time-aware collaborative filtering technique that integrates and utilizes the neighbors of each item and each user, weighting the recent similarity more than the past similarity with them, and reflecting it in the recommendation list decision. Through the experimental evaluation, it was confirmed that the proposed method showed superior performance in terms of prediction accuracy than other existing methods.

• Journal of the Korea Academia-Industrial cooperation Society
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• v.17 no.3
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• pp.699-707
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• 2016

This paper proposes a low-complexity central processing unit (CPU) that is suitable for deeply embedded systems, including Internet of things (IoT) applications. The core features a 16-bit instruction set architecture (ISA) that leads to high code density, as well as a multicycle architecture with a counter-based control unit and adder sharing that lead to a small hardware area. A co-processor, instruction cache, AMBA bus, internal SRAM, external memory, on-chip debugger (OCD), and peripheral I/Os are placed around the core to make a system-on-a-chip (SoC) platform. This platform is based on a modified Harvard architecture to facilitate memory access by reducing the number of access clock cycles. The SoC platform and CPU were simulated and verified at the C and the assembly levels, and FPGA prototyping with integrated logic analysis was carried out. The CPU was synthesized at the ASIC front-end gate netlist level using a $0.18{\mu}m$ digital CMOS technology with 1.8V supply, resulting in a gate count of merely 7700 at a 50MHz clock speed. The SoC platform was embedded in an FPGA on a miniature board and applied to deeply embedded IoT applications.

• Journal of Digital Contents Society
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• v.10 no.4
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• pp.493-499
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• 2009

Three methods frequently used for Hangul display in computer systems are Standard Johab Code in which each of Hangul consonants and vowels is given a 5-bit code and each syllable created by combining them forms a 2-byte code, Standard Wansung Code in which each of all the syllables generally used for Hangul presentation forms a 2-byte code, and Unicode in which each syllable in most of the world's language systems is given a unique code so that it allows computers to consistently represent and manipulate them in a unified manner. An embedded system in general has a lower processing power and a limited amount of storage space, compared to a personal compute(PC) system. According to its usage, however, the former may have a processing power equal to that of the latter. Hence, when Hangul display needs to be adopted, an embedded system must choose a display method suitable for its own resource environment. This paper introduces a TFT LCD initialization method and pixel display functions of an LN2440SBC embedded board on which an LP35, a 3.5" TFT LCD kit, is attached. Using the initialization and pixel display functions, in addition, we compare three aforementioned Hangul display methods, in terms of their processing speeds and amounts of memory space required. According to experiments, Standard Johab Code requires less amount of memory space but more processing time than Standard Wansung Code, and Unicode requires the largest amount of memory space but the least processing time.