• The Journal of the Acoustical Society of Korea
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• 제23권8호
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• pp.554-561
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• 2004

As the technologies of semiconductor and multimedia communication have been improved. the high-quality video and the multi-channel audio have been highlighted. MPEG Audio Layer 3 decoder has been implemented as a Processor using a standard. Since the synthesis filter of MPEG-1 Audio Layer 3 decoder requires the most outstanding operation in the entire decoder. the synthesis filter that can reduce the amount of operation is needed for the design of the high-speed processor. Therefore, in this paper, the synthesis filter. the most important part of MPEG Audio, is materialized in FPGA using the method of DAULT (distributed arithemetic look-up table). For the design of high-speed synthesis filter, the DAULT method is used instead of a multiplier and a Pipeline structure is used. The Performance improvement by 30% is obtained by additionally making the result of multiplication of data with cosine function into the table. All hardware design of this Paper are described using VHDL (VHIC Hardware Description Language) Active-HDL 6.1 of ALDEC is used for VHDL simulation and Synplify Pro 7.2V is used for Model-sim and synthesis. The corresponding library is materialized by XC4013E and XC4020EX. XC4052XL of XILINX and XACT M1.4 is used for P&R tool. The materialized processor operates from 20MHz to 70MHz.

• Journal of the Institute of Electronics Engineers of Korea SD
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• 제45권2호
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• pp.82-92
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• 2008

Recently, many digital signal processing(DSP) applications such as H.264, CDMA and MP3 are predominant tasks for modern high-performance portable devices. These applications are generally computation-intensive, and therefore, require quite complicated accelerator units to improve performance. Designing such specialized, yet fixed DSP accelerators takes lots of effort. Therefore, DSPs with multiple accelerators often have a very poor time-to-market and an unacceptable area overhead. To avoid such long time-to-market and high-area overhead, dynamically reconfigurable DSP architectures have attracted a lot of attention lately. Dynamically reconfigurable DSPs typically employ a multi-functional DSP accelerator which executes similar, yet different multiple kinds of computations for DSP applications. With this type of dynamically reconfigurable DSP accelerators, the time to market reduces significantly. However, integrating multiple functionalities into a single IP often results in excessive control and area overhead. Therefore, delay and power consumption often turn out to be quite excessive. In this thesis, to reduce power consumption of dynamically reconfigurable IPs, we propose a novel fine-grained clock gating scheme, and to reduce size of dynamically reconfigurable IPs, we propose a compact multiplier-less multiplication unit where shifters and adders carry out constant multiplications.

• Journal of Broadcast Engineering
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• 제25권4호
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• pp.497-506
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• 2020

A chameleonic surface proposed in this study was a pin-art and 3D display device for generating arbitrary shapes. A smooth and continuous surface was formed using slim telescopic actuators and high-elasticity composite material. Realistic 3D shapes were continuously generated by projecting dynamic mapping images on the surface. A slim telescopic actuator was designed to show long strokes and minimize area for staking. A 3D shape was formed by thrusting and extruding the high-elasticity material using multiple telescopic actuators. This structure was advantageous for generating arbitrary continuous surface, projecting dynamic images and lightening weight. Because of real-time synchronization, a distributed controller based on EtherCAT was applied to operate hundreds of telescopic actuators smoothly. Integrated operating software consecutively generated realistic scenes by coordinating extruded shapes and projecting 3D image from multiple projectors. An opera content was optimized for the chameleon surface and showed to an audience in an actual concert.

• Journal of Broadcast Engineering
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• 제18권2호
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• pp.204-214
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• 2013

Recently various research have been conducted relating to the implementation of signal processing or communication system by software using the massively parallel processing capability of the GPU. In this work, we focus on reducing software simulation time of 2K/8K FFT in DVB-T by using GPU. we estimate the processing time of the DVB-T system, which is one of the standards for DTV transmission, by CPU. Then we implement the FFT processing by the software using the NVIDIA's massively parallel GPU processor. In this paper we apply stream process method to reduce the overhead for data transfer between CPU and GPU, coalescing method to reduce the global memory access time and data structure design method to maximize the shared memory usage. The results show that our proposed method is approximately 20~30 times as fast as the CPU based FFT processor, and approximately 1.8 times as fast as the CUFFT library (version 2.1) which is provided by the NVIDIA when applied to the DVB-T 2K/8K mode FFT.

• Journal of KIISE:Computer Systems and Theory
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• 제32권11_12호
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• pp.629-638
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• 2005

In the System on a Chip design, the on chip bus is one of the critical factors that decides the overall system performance. Especially, in the case or reusing the IPs such as processors, DSPs and multimedia IPs that requires higher bandwidth, the bandwidth problems of on chip bus are getting more serious. Recently ARM proposes the Multi-Layer AHB BusMatrix that is a highly efficient on chip bus to solve the bandwidth problems. The Multi-Layer AHB BusMatrix allows parallel access paths between multiple masters and slaves in a system. This is achieved by using a more complex interconnection matrix and gives the benefit of increased overall bus bandwidth, and a more flexible system architecture. However, there is one clock cycle delay for each master in existing Multi-Layer AHB BusMatrix whenever the master starts new transactions or changes the slave layers because of the Input Stage and arbitration logic realized with Moore type. In this paper, we improved the existing Multi-Layer AHB BusMatrix architecture to solve the one clock cycle delay problems and to reduce the area overhead of the Input Stage. With the elimination of the Input Stage and some restrictions on the arbitration scheme, we tan take away the one clock cycle delay and reduce the area overhead. Experimental results show that the end time of total bus transaction and the average latency time of improved Multi-Layer AHB BusMatrix are improved by $20\%\;and\;24\%$ respectively. in ease of executing a number of transactions by 4-beat incrementing burst type. Besides the total area and the clock period are reduced by $22\%\;and\;29\%$ respectively, compared with existing Multi-layer AHB BusMatrix.

• Journal of KIISE:Information Networking
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• 제29권6호
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• pp.722-737
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• 2002

As the number of multimedia applications increases, various protocols and architectures have been proposed to provide QoS(Quality of Service) guarantees in the Internet. Most of these techniques, though, bear inherent contradiction between the scalability and the capability of providing QoS guarantees. In this paper, we propose a protocol, named DQSP(Dynamic QoS Support Protocol), which provides the dynamic resource allocation and admission control for QoS guarantees in a scalable way. In DQSP, the core routers only maintain the per source-edge router resource allocation state information. Each of the source-edge routers maintains the usage information for the resources allocated to itself on each of the network links. Based on this information, the source edge routers perform admission control for the incoming flows. For the resource reservation and admission control, DQSP does not incur per flow signaling at the core network, and the amount of state information at the core routers depends on the scale of the topology instead of the number of user flows. Simulation results show that DQSP achieves efficient resource utilization without incurring the number of user flow related scalability problems as with IntServ, which is one of the representative architectures providing end-to-end QoS guarantees.

• Journal of Broadcast Engineering
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• 제5권1호
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• pp.113-122
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• 2000

It is sometimes necessary to remove the captions and recover original images from video images already broadcast, When the number of images requiring such recovery is small, manual processing is possible, but as the number grows it would be very difficult to do it manually. Therefore, a method for recovering original image for the caption areas in needed. Traditional research on image restoration has focused on restoring blurred images to sharp images using frequency filtering or video coding for transferring video images. This paper proposes a method for automatically recovering original image using BMA(Block Matching Algorithm). We extract information on caption regions and scene change that is used as a prior-knowledge for recovering original image. From the result of caption information detection, we know the start and end frames of captions in video and the character areas in the caption regions. The direction for the recovery is decided using information on the scene change and caption region(the start and end frame for captions). According to the direction, we recover the original image by performing block matching for character components in extracted caption region. Experimental results show that the case of stationary images with little camera or object motion is well recovered. We see that the case of images with motion in complex background is also recovered.

• Journal of KIISE:Software and Applications
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• 제30권1_2호
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• pp.19-30
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• 2003

Based upon XML, a standard document format on the web, there have been many active studies on e-Commerce, wireless communication, multimedia technology and so forth. JML is an XML application suitable for understanding and reusing the source code written using JAVA for various purposes. And it is a DTD which can effectively express various information related to hierarchical class structures, class/method relationships and so on. This paper describes a tool which generates JML document by extracting a comment information from Java source code and information helpful for reusing and understanding by JML in terms of the reverse engineering and a tool which generates a skeleton code of Java application program from the document information included in the automatically or manually generated JML document in terms of the forward engineering. By using the result of this study, the information useful and necessary for understanding, analyzing or maintaining the source code can be easily acquired and the document of XML format makes it easy for developers and team members to share and to modify the information among them. And also, the Java skeleton coed generated form JML documents is a reliable robust code, which helps for developing a complete source code and reduces the cost and time of a project.

• The Journal of Society for e-Business Studies
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• 제16권4호
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• pp.197-220
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• 2011

The smartphone is simply beyond the means of communication equipment, to line up the turning point of mobile convergence, is recognized as a service tool of new concept the camera, game, multimedia function, digital multimedia broadcasting, mobile internet etc, that use of smartphone is working toward developed a variety and new business models. The study is empirically studied casualties that self-determination influences flow and satisfaction which is intrinsic motivation of smartphone. There are many studies on flow, is intrinsic motivation, influencing satisfaction and Loyalty, but there are little studies which variables influences flow. this study is explore causality of autonomy, competence, relatedness which are major variables of self-determination theory that studied factors effecting intrinsic motivation influencing flow and satisfaction. This study developed a research model to explain the use of smartphone, and collected 670 survey responses from the office workers of seoul S company who had experiences with such smartphone. To prove the validity of the proposed research model, SEM analysis is applied with valid 670 questionnaires. The results, firstly, autonomy positively influences flow. secondly, competence significantly influences flow. thirdly, relatedness significantly influenced flow. also, upper above results shows that flow influences satisfaction.

• The Transactions of the Korea Information Processing Society
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• 제5권12호
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• pp.3047-3062
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• 1998

This paper deseribes the desihn and the implementation of the Realtime Transport Protocol(RTP)/ Rdaltime Control Protocol(RTCP) (RFC 1889,1890) that is used to transmit the audio/video data to any destination and to feedback the Quality of Service (QoS) information of the received media data to the sender, in the teleconferencing systems proposed by ITU-T. These protocols are implemented with multi thead technique and run on top of UDP/IP-Multicast through the socket interface as the underlying protocol. The upper layer is impelmented such that in can be accessed by the H245 comference control protocol. The RTP packetizes the digitized audio/video data from the encoder info a fixed format, and multieast to the participants. The RTCP monitors RTP packets and extracts the QoS values from it such as round-trip delay, jiter and packet loss to form RTCP packets and non periokically sends them to the sender site. In this Paper, we also descritx the study of measurement and analysis for QoS factors that observed on performing teleconferencing system over Internet. The results from this experiment is indicate that RTT and Jitter value are acceptable even entwork load is high. However, it appears that packet loss rate is high in daytime and most losses periods have length one or two.