• Journal of the Institute of Electronics Engineers of Korea SD
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• v.47 no.8
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• pp.29-35
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• 2010

In this paper we propose a new pattern generator for a BIST architecture that can reduce the power consumption during test application. The principle of the proposed method is to reconstruct an LFSR circuit to reduce WSAs of the heavy nodes by suppressing the heavy inputs. We propose algorithms for finding heavy nodes and heavy inputs. Using the Modified LFSR which consists of some AND/OR gates trees and an original LFSR, BIST applies modified test patterns to the circuit under test. The proposed BIST architecture with small hardware overhead effectively reduces the average power consumption during test application while achieving high fault coverage. Experimental results on the ISCAS benchmark circuits show that average power reduction can be achieved up to 30.5%.

• Journal of KIISE:Computing Practices and Letters
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• v.16 no.12
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• pp.1239-1243
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• 2010

The web environment is evolving rapidly. Testing in the web based software is an essential process to improve stability and productivity. Testing of complex web contents and ill(user interface) is most important thing. Implemented test cases are efficient when they are automated and reusable. But, most of the testing automation tools are focused on technical accessibility and functions still. A collaboration of the persons concerned and reusability of implemented test case are ignored. In this paper we propose an efficient way to design automated test case in web environment, and to share and pattern automated test cases we introduce testing framework called NTAF(NHN Test Automation Framework.). The NTAF is based on open source framework. It provides integrated testing environment that web testing cane be automated and managed continuously.

• Proceedings of the Korean Information Science Society Conference
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• 2004.10b
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• pp.763-765
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• 2004

본 연구는 간경변을 보유한 환자의 복부 CT 영상을 이용하여 비장의 웨이브 패턴(wave pattern)을 관찰하였는데 정상간을 보유한 환자의 복부 CT 영상과 차이가 있음을 발견하였다. 본 논문은 관찰된 두 가지 원리를 바탕으로 복부 CT 영상에서 비장의 웨이브 패턴을 이용하여 간경변을 효과적으로 진단하는 새로운 방법을 제시한다. 본 논문에서 실험에 사용한 영상들의 경우에 꼬리엽과 우엽의 비율로써 간경변을 보유한 영상임을 알 수 있는 경우에는 모두 비장의 웨이브 패턴 테스트들로써 간경변 보유 판정 결과를 얻었다. 이는 꼬리엽과 우엽의 비율 테스트를 생략하고 비장만으로 간경변 보유간을 판정해 낼 수 있음을 말해주는 것이다.

• Journal of the Institute of Electronics Engineers of Korea SD
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• v.41 no.2
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• pp.55-65
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• 2004

In this paper, An efficient non-scan DFT method for datapaths described in RTL is proposed. The proposed non-scan DFT method improves testability of datapaths based on hierarchical testability analysis regardless to width of the datapath. It always guarantees higher fault efficiency and faster test pattern generation time with little hardware overhead than previous methods. The experimental result shows the superiority of the proposed method of test pattern generation time, application time, and area overhead compared to the scan method.

• Journal of the Institute of Electronics Engineers of Korea SD
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• v.45 no.9
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• pp.33-40
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• 2008

As the speed of memory is improved vey fast the advanced test equipments are needed to test the ultra-high speed memory devices efficiently. It is necessary to develop the Algorithmic Pattern Generator (ALPG) that tests fast memory devices effectively using the instructions that testers want to use. In this paper, we propose a new parallel ALPG for the ultra-high speed memory testing. The proposed ALPG can generate patterns for fast memory devices at high speed using manual instructions by the Instruction Analyzer.

• Journal of the Institute of Electronics Engineers of Korea SD
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• v.45 no.1
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• pp.14-19
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• 2008

Semiconductor testing area challenges many testing issues due to the minimization and ultra high performance of current semiconductors. Among these issues, signal integrity test on interconnections must be solved for highly integrated circuits like SoC. In this paper, we propose an effective pattern application method for signal integrity test on interconnects. Proposed method can be applied by using boundary scan architecture and very efficient test can be preceded with pretty short test time.

• Journal of KIISE:Computer Systems and Theory
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• v.30 no.2
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• pp.99-107
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• 2003

This paper proposes a design for testability (DFT) and testability analysis method for register-transfer level (RTL) circuits. The proposed method executes testability analysis - controllability and observability - on the RTL circuit and determines the insertion points to enhance the testability. Then with the associated priority based on the testability, we insert only a few of the test multiplexers resulting in minimized area overhead. Experimental results shows a higher fault coverage and a shorter test generation time than the scan method. Also, the proposed method takes a shorter test application time required.

• Proceedings of the Korea Information Processing Society Conference
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• 2003.05a
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• pp.591-594
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• 2003

본 논문에서는 hopfield 신경망을 사용한 다양한 부분적인 패턴 복원에 관하여 연구하였다. 여섯 개의 $32{\times}32$ 비트맵 훈련패턴들은 한글자음 ㄱ, ㅁ, ㅂ, ㅇ, ㅊ, ㅍ, 그리고 남자와 여자 이미지로 구성되어 있다. 그리고 부분패턴들의 크기, 범위, 방향의 효과를 알아보기 위해서 훈련패턴에서 여덟 가지 형태의 테스트 패턴을 만든다. 한글 자음의 경우 유사 패턴이 많기 때문에 완전히 복원되지 못하였으나, 400회 정도 수렵된 후에는 테스트패턴들이 견본패턴과 비슷한 모양으로 복원되었다. 이 유사도를 측정하기 위해 해밍거리 (Hamming distance)를 이용하였다. 유사도를 측정하여 해밍거리가 가장 적은 것으로 본래의 이미지들 복원하였다.

• Proceedings of the KIEE Conference
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• 2009.07a
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• pp.1893_1894
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• 2009

S/W 화이트박스 단위 테스트 시에 교호강도의 수를 결정해야 하는데 이를 소스에서 함수의 인자가 어떤 식으로 사용되는지를 분석하여 자동으로 결정할 수 있는 방법이 있다. 소스 상에서 인자 사용의 패턴을 분석하여 특정 패턴이 되면 강도수를 늘리고 최종적으로 교호 강도 수를 결정할 수 있게 된다. 본 논문에서는 이를 위해 조합 강도 결정 테이블을 작성하여 이를 이용한 테스트 교호 강도 수 결정 방법을 제시한다.

• Journal of the Institute of Electronics and Information Engineers
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• v.50 no.6
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• pp.122-130
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• 2013

The demand and the supply are increasing sharply in accordance with the growth of the Memory Semiconductor Industry. The Flash Memory above all is being utilized substantially in the Industry of smart phone, the tablet PC and the System on Chip (SoC). The Flash Memory is divided into the NOR-type Flash Memory and the NAND-type Flash Memory. A lot of study such as the Built-In Self Test (BIST), the Built-In Self Repair (BISR) and the Built-In Redundancy Analysis (BIRA), etc. has been progressed in the NOR-type fash Memory, the study for the Built-In Self Test of the NAND-type Flash Memory has not been progressed. At present, the pattern test of the NAND-type Flash Memory is being carried out using the outside test equipment of high price. The NAND-type Flash Memory is being depended on the outside equipment as there is no Built-In Self Test since the erasure of block unit, the reading and writing of page unit are possible in the NAND-type Flash Memory. The Built-In Self Test equipped with 2 kinds of finite state machine based structure is proposed, so as to carry out the pattern test without the outside pattern test equipment from the NAND-type Flash Memory which carried out the test dependant on the outside pattern test equipment of high price.