• Journal of the Institute of Electronics Engineers of Korea SD
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• v.47 no.11
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• pp.30-36
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• 2010

In recent memories, repair is an unavoidable method to maintain its yield and quality. Although many word oriented memories as well as embedded memories in system-on-chip (SOC) consists of multiple local memory blocks with a global spare architecture, most of previous studies on built-in redundancy analysis (BIRA) algorithms have focused on single memory block with a local spare architecture. In this paper, a new BIRA algorithm for multiple blocks with a global spare architecture is proposed. The proposed BIRA is basd on CRESTA which is able to achieve optimal repair rate with almost zero analysis time. In the proposed BIRA, all repair solutions for local memory blocks are analyzed by local analyzers which belong to each local memory block and then compared sequentially and judged whether each solution can meet the limitation of the global spare architecture or not. Experimental results show that the proposed BIRA achieves much faster analysis speed compared to previous BIRAs with an optimal repair rate.

• Proceedings of the Korean Institute of Information and Commucation Sciences Conference
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• 2011.05a
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• pp.136-139
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• 2011

The conventional semiconductor equipment has adopted SRAM module as the test pattern memory, which has a simple design and does not require refreshing. However, SRAM has its disadvantages as it takes up more space as its capacity becomes larger, making it difficult to meet the requirements of large memories and compact size. if DRAM is adopted as the semiconductor inspection equipment, it takes up less space and costs less than SRAM. However, DRAM is also disadvantageous because it requires the memory cell refresh, which is not suitable for the semiconductor examination equipments that require correct timing. Therefore, In this paper, we will proposed an algorithm for punctuality guarantee of memory-free inspection equipment using DDR2 SDRAM. And we will produced memory controller using punctuality guarantee algorithm.

• Journal of the Institute of Electronics Engineers of Korea SD
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• v.49 no.3
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• pp.21-29
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• 2012

This paper presents optimized searching technique to improve the performance of H.264/AVC. By using the proposed forward and backward searching algorithm, redundant cycles of latency for data reordering can be removed. Furthermore, in order to reduce the total number of execution cycles of CAVLC encoder, early termination mode and two stage pipelined architecture are proposed. The experimental result shows that the proposed architecture needs only 36.0 cycles on average for each $16{\times}16$ macroblock encoding. The proposed architecture improves the performance by 57.8% than that of previous designs. The proposed CAVLC encoder was implemented using Verilog HDL and synthesized with Magnachip $0.18{\mu}m$ standard cell library. The synthesis result shows that the gate count is about 17K with 125Mhz clock frequency.

• Journal of IKEEE
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• v.23 no.4
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• pp.1366-1372
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• 2019

In this paper, we designed a revised neural network to remove the Monte Carlo Rendering noise contained in the ray tracing graphics. The Monte Carlo Rendering is the best way to enhance the graphic's realism, but because of the need to calculate more than thousands of light effects per pixel, rendering processing time has increased rapidly, causing a major problem with real-time processing. To improve this problem, the number of light used in pixels is reduced, where rendering noise occurs and various studies have been conducted to eliminate this noise. In this paper, a deep learning is used to remove rendering noise, especially by separating the rendering image into diffuse and specular light, so that the structure of the dual neural network is designed. As a result, the dual neural network improved by an average of 0.58 db for 64 test images based on PSNR, and 99.22% less light compared to reference image, enabling real-time race-tracing rendering.

• Journal of the Institute of Electronics Engineers of Korea SD
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• v.37 no.3
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• pp.55-61
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• 2000

This paper presents an efficient hardware architecture of frame memory interface in MPEG-2 video encoder. To reduce the size of memory buffers between SDRAM and the frame memory module, the number of clocks needed for each memory access is minimized with dual bank operation and burst length change. By allocating the remaining cycles not used by SDRAM access, to the random access cycle, the internal buffer size, the data bus width, and the size of the control logic can be minimized. The proposed architecture is operated with 54MHz clock and designed with the VT $I^{тм}$ 0.5 ${\mu}{\textrm}{m}$ CMOS TLM standard cell library. It is verified by comparing the test vectors generated by the c-code model with the simulation results of the synthesized circuit. The buffer area of the proposed architecture is reduced to 40 % of the existing architecture.

• Journal of the Institute of Electronics Engineers of Korea SD
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• v.40 no.4
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• pp.85-94
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• 2003

The asynchronous design methods proved to have the higher performance in power consumption and execution speed than synchronous ones because it just needs to activate the required module without feeding clock in the system. Despite the advantage of CISC machine providing the variable addressing modes and instructions, its execution scheme is hardly suited for a synchronous Pipeline architecture and incurs a lot of overhead. This paper proposes a novel asynchronous pipeline architecture, A80sl, whose instruction set is fully compatible with that of Intel 80C51, an embedded micro controller. We classify the instructions into the group keeping the same execution scheme for the asynchronous pipeline and optimize it eliminating the bubble stage that comes from the overhead of the multi-cycle execution. The new methodologies for branch and various instruction lengths are suggested to minimize the number of states required for instructions execution and to increase its parallelism. The proposed A80C51 architecture is synthesized with 0.35${\mu}{\textrm}{m}$ CMOS standard cell library. The simulation results show higher speed than that of Intel 80C51 with 36 MHz and other asynchronous counterparts by 24 times.

• Korean Chemical Engineering Research
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• v.49 no.1
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• pp.10-14
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• 2011

The electrode material performances of electric double layer capacitor(EDLC) were investigated using mesopous active carbon fiber(ACF), which was prepared by the iron exchange method. The mesoporous ACF had pore characteristics of specific surface area around 1249, 664 $m^2$/g, mesoporous fraction around 70.6-81.3% and meanpore size around 2.78-4.14 nm. The results showed that as HNO3 treatment time decreased, the specific surface area increased and mesoporous fraction decreased. To investigate electrochemical performance of EDLC, unit cell was manufactured using mesoporus ACF, conducting material and binder; organic elctrolyte was used on this experiment. The specific capacitance of ACF treated with HNO3 for 2 hours turned out to be 0.47 $F/cm^2$and the results of the cyclic charge-discharge tests were stable. Thus, the electrochemical performance of EDLC was mainly dependent on specific surface area of ACF electrode and the diffusion resistance of charge decreased as the mesopore increased.

• Journal of the Korean Institute of Intelligent Systems
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• v.9 no.6
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• pp.634-643
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• 1999

This paper concerns an implementation of f~rry logic controller (FLC') on a reconfigurahle FP

• Transactions of the Korean Society of Mechanical Engineers A
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• v.37 no.10
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• pp.1305-1313
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• 2013

In this study, a method to apply feature-based simplification to boundary representation models is proposed. For feature-based simplification, a volume decomposition tree is created from a boundary representation model. The volume decomposition tree is represented by regularized Boolean operations of additive volumes, subtractive volumes, and fillet/round/chamfer volumes, and it is generated by stepwise volume decomposition, which consists of fillet/round/chamfer decomposition, wrap-around decomposition, volume split decomposition, and cell-based decomposition. After the volume decomposition tree is transformed to an infix expression, the CAD model can be simplified by reordering the volumes. To verify the proposed method, a prototype system was implemented, and experiments on test cases were conducted. From the results of the experiments, it is verified that the proposed method is useful for simplifying CAD models based on boundary representation.

• Applied Chemistry for Engineering
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• v.25 no.6
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• pp.592-597
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• 2014

The graphite/$SiO_2$ composites as anode materials for lithium-ion batteries were prepared by sol-gel method to improve the graphite's electrochemical characteristics. The prepared graphite/$SiO_2$ composites were analysed by XRD, FE-SEM and EDX. The graphite surface modified by silicon dioxide showed several advantages to stabilize SEI layer. The electrochemical characteristics were investigated for lithium ion battery using graphite/$SiO_2$ as the working electrode and Li metal as the counter electrode. Electrochemical behaviors using organic electrolytes ($LiPF_6$, EC/DMC) were characterized by charge/discharge, cycle, cyclic voltammetry and impedance tests. The lithium ion battery using graphite/$SiO_2$ electrodes had better capacity than that of using graphite electrodes and was able to deliver a discharge capacity with 475 mAh/g at a rate of 0.1 C. Also, the capacity retention ratio of the modified graphite reaches 99% at a rate of 0.8 C.