• Proceedings of the Korean Institute of Information and Commucation Sciences Conference
• /
• 2016.05a
• /
• pp.445-447
• /
• 2016

Performance comparison between Tunneling Field-Effect Transistors (TFETs) was examined when three types of device parameter of double-gate TFET (DG-TFET) and single-gate TFET (SG-TFET) are varied. When the channel length is over 30 nm, silicon thickness is below 20 nm, and a gate insulator thickness decreases, the performance of $I_{on}$ and SS in SG-TFETs and DG-TFETs enhances. It shows that the performance of the DG-TFETs is improved than that of SG-TFETs at three types of device parameter.

• Journal of the Institute of Electronics Engineers of Korea TE
• /
• v.39 no.4
• /
• pp.335-340
• /
• 2002

In this paper, the stress induced leakage currents of thin silicon oxides is investigated in the ULSI implementation with nano structure transistors. The stress and transient currents associated with the on and off time of applied voltage were used to measure the distribution of high voltage stress induced traps in thin silicon oxide films. The stress and transient currents were due to the charging and discharging of traps generated by high stress voltage in the silicon oxides. The transient current was caused by the tunnel charging and discharging of the stress generated traps nearby two interfaces. The stress induced leakage current will affect data retention in electrically erasable programmable read only memories. The oxide current for the thickness dependence of stress current, transient current, and stress induced leakage currents has been measured in oxides with thicknesses between 113.4${\AA}$ and 814${\AA}$, which have the gate area $10^3cm^2$. The stress induced leakage currents will affect data retention and the stress current, transient current is used to estimate to fundamental limitations on oxide thicknesses.

• Proceedings of the Korean Vacuum Society Conference
• /
• 2012.02a
• /
• pp.302-302
• /
• 2012

최근 비 휘발성 메모리 시장의 확대와 수요가 많아지면서, 비휘발성 메모리 소자의 제작에 대한 연구가 활발히 진행되고 있다. 특히, 실리사이드 나노입자를 적용한 소자는 현 실리콘 기반의 반도체 공정의 적용이 용이하다. 따라서 본 연구에서는 실리사이드 계열의 화합물 중에서 일함수가 4.63 eV인 Vanadium silicide (V3Si) 나노입자 메모리소자를 제작하여 전기적 특성과 열 안정성에 대하여 알아보았다. p-Si기판에 약 6nm 두께의 SiO2 터널층을 건식 산화 방법으로 성장시킨 후 V3Si 나노입자를 제작하기 위해서 V3Si 금속박막을 스퍼터링 방법으로 4 nm~6 nm의 두께로 터널 절연막 위에 증착시켰다. 그리고 컨트롤 절연막으로 SiO2를 초고진공 스퍼터를 이용하여 50 nm 증착하였고, 급속 열처리 방법으로 질소 분위기에서 $800^{\circ}C$의 5초 동안 열처리하여 V3Si 나노 입자를 형성하였다. 마지막으로 200 nm두께의 Al을 증착하고, 리소그래피 공정을 통하여 채널 길이와 너비가 각각 $2{\mu}m$, $5{\mu}m$, $10{\mu}m$를 가지는 트랜지스터를 제작하였다. 제작된 시편의 V3Si 나노입자의 크기와 균일성은 투과 전자 현미경으로 확인하였고, 후 열처리 공정 이후 V3Si의 존재여부의 확인을 위해서 X-ray 광전자 분광법의 표면분석기술을 이용하여 확인하였다. 소자의 전기적인 측정은 Agilent E4980A LCR meter, 1-MHz HP4280A와 HP 8166A pulse generator, HP4156A precision semiconductor parameter analyzer을 이용하여 측정온도를 $125^{\circ}C$까지 변화시키면서 전기적인 특성을 확인하였다. 본 연구에서는 온도에 선형적 의존성을 가지는 전하누설 모델인 T-model 을 이용하여 나노입자 비휘발성 메모리소자의 전하누설 근원을 확인한 후, 메모리 소자의 동작 특성과의 물리적인 연관성을 논의하였다. 이를 바탕으로 나노입자 비휘발성 메모리소자의 열적안정성을 확보하고 소자 특성향상을 위한 최적화 구조를 제안하고자 한다.

• Journal of the Korea Institute of Information and Communication Engineering
• /
• v.7 no.2
• /
• pp.269-275
• /
• 2003

Polysilicon-oxide-nitride-oxide-silicon(SONOS) transistors were fabricated by using 0.35${\mu}{\textrm}{m}$ complementary metal-oxide-semiconductor(CMOS) process technology to realize a low voltage programmable flash memory. The thickness of the tunnel oxide, the nitride, and the blocking oxide were 2.4nm, 4.0nm, and 2.5nm, respectively, and the cell area of the SONOS memory was 1.32$\mu$$m^2$. The SONOS device revealed a maximum memory window of 1.76V with a switching time of 50ms at 10V programming, as a result of the scaling effect of the nitride. In spite of scaling of nitride thickness, memory window of 0.5V was maintained at the end of 10 years, and the endurance level was at least 105 program/erase cycles. Over-erase, which was shown seriously in floating gate device, was not shown in SONOS device.

• Journal of the Institute of Electronics Engineers of Korea SD
• /
• v.42 no.9 s.339
• /
• pp.9-18
• /
• 2005

To make high-performance, low-power transistors beyond the technology node of 60 nm complementary metal-oxide-semiconductor field-effect transistors(C-MOSFETs) possible, the effect of electron mobility of the thickness of strained Si grown on a relaxed SiGe/SiO2/Si was investigated from the viewpoint of mobility enhancement via two approaches. First the parameters for the inter-valley phonon scattering model were optimized. Second, theoretical calculation of the electronic states of the two-fold and four-fold valleys in the strained Si inversion layer were performed, including such characteristics as the energy band diagrams, electron populations, electron concentrations, phonon scattering rate, and phonon-limited electron mobility. The electron mobility in an silicon germanium on insulator(SGOI) n-MOSFET was observed to be about 1.5 to 1.7 times higher than that of a conventional silicon on insulator(SOI) n-MOSFET over the whole range of Si thickness in the SOI structure. This trend was good consistent with our experimental results. In Particular, it was observed that when the strained Si thickness was decreased below 10 nm, the phonon-limited electron mobility in an SGOI n-MOSFT with a Si channel thickness of less than 6 nm differed significantly from that of the conventional SOI n-MOSFET. It can be attributed this difference that some electrons in the strained SGOI n-MOSFET inversion layer tunnelled into the SiGe layer, whereas carrier confinement occurred in the conventional SOI n-MOSFET. In addition, we confirmed that in the Si thickness range of from 10 nm to 3 nm the Phonon-limited electron mobility in an SGOI n-MOSFET was governed by the inter-valley Phonon scattering rate. This result indicates that a fully depleted C-MOSFET with a channel length of less than 15 m should be fabricated on an strained Si SGOI structure in order to obtain a higher drain current.