• Journal of the Korea Institute of Information and Communication Engineering
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• v.7 no.1
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• pp.69-74
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• 2003

In this paper, we propose the synchronization recovery algorithm which is suitable to wireless Multimedia of wireless channel situation which is being used OFDM signaling method. The basic of the suggested clock synchronization. restoration Algorithm is to getting the shock response of channel or getting the multipath strength profile through IFTT after the getting the frequency, response of deducted channel from channel deducted of receiver and to trace the location in the channel energy concentrated area of timing area. And it also analysis the start point of 64-QAM and 16-QAM if the sampling clock offset has the sample of ${\pm}$ 1-3, and we identified the occurance of performance deterioration when occures more than 2 samples of offset to compare with star point and BER performance in optimum sampling point result of BER performance checking, and we know that the recovery algorithm proposed algorithm also provide excellent synchronization characteries under frequency, selecting fading channel as result of simulation.

• The Journal of Korean Institute of Communications and Information Sciences
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• v.39B no.5
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• pp.296-303
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• 2014

Reference Broadcast Synchronization (RBS) is one of the most prominent synchronization protocols in wireless sensor nework. Given that the broadcasting medium is available, RBS can give very high accuracy of synchronization. However, RBS uses instantaneous synchronization and results in time discontinuity, which might cause serious faults in the distributed system. Also, RBS lacks packet loss tolerance, which brings about degraded performance in severe conditions of wireless channel. In this paper, the problem of time discontinuity in RBS is pointed out and the effect of packet loss on the performance of RBS is examined. Then, a continuous synchronization and a packet loss tolerance mechanism for RBS are proposed, and the result is verified through simulations.

• Proceedings of the Korea Information Processing Society Conference
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• 2005.05a
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• pp.481-484
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• 2005

본 논문에서는 부동소수점 연산을 사용하면서도 빠른 처리속도를 가지는 신경망의 파이프라인 설계를 제안한다. 부동소수점 연산은 고정소수점 연산보다 느린 처리속도와 많은 면적으로 일반적인 하드웨어 구현에서 잘 사용되지 않지만, 제안된 구조에서는 고정소수점 연산보다 더 정확한 값을 계산할 수 있는 부동소수점 연산을 사용하며 부동소수점의 느린 처리 속도를 보완할 수 있도록 파이프라인 구조를 사용한다. 파이프라인 구조의 성능을 검증하기 위해 2 가지의 서로 다른 구조의 신경망을 사용한다. 실험 환경으로는 Xilinx XC2V8000 칩과 Xilinx ISE 6.2 의 합성 도구를 사용한다. 실험 결과는 파이프라인 구조일 때의 신경망은 각각 7 클럭, 8 클럭이 소요되고, 파이프라인 구조가 아닐 때 각각의 신경망은 77 클럭, 84 클럭으로써 파이프라인 구조일 때 약 10 배의 빠른 처리를 가진다.

• Proceedings of the Korean Institute of Navigation and Port Research Conference
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• v.2
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• pp.419-422
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• 2006

위성발사체와 같이 극환 환경에서 사용되는 전자 탑재물들은 진동이나 충격이 가해질 때 정상적으로 동작하지 못하는 경우가 많다. 그러므로 위성발사체에 탑재되는 모든 탑재물들은 발사전에 지상에서 다양한 환경시험을 통하여 그 성능을 검증해야 한다. 기준 클럭을 사용하여 항법해를 계산해야 하는 GPS 수신기는 특히 다른 전자 탑재물 보다 클럭의 안정도에 더 많은 영향을 받으므로 극한 진동 및 충격 환경에서 다양한 문제들이 나타난다. 본 논문에서는 위성발사체의 비행안전용으로 개발된 GPS 수신기의 진동 및 충격 환경시험 결과를 바탕으로 그러한 환경에서 기준 클럭이 영향을 받아 나타나는 다양한 동작특성을 설명하고, 기준 클럭의 중요성과 진동 및 충격 환경시험에서의 유의사항 및 문제 해결 방법에 대하여 설명한다.

• The Journal of the Korea institute of electronic communication sciences
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• v.10 no.10
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• pp.1123-1130
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• 2015

Network on a chip(NoC) is a communication subsystem between intellectual property(IP) cores in a SoC and improves high performance in the scalability and the power efficiency compared with conventional buses and crossbar switches. NoC needs a synchronizer to overcome the metastability problem between data links. This paper presents a new mesochronous synchronizer(MS) which is composed of selection window generator, selection signal generator, and data buffer. A delay line circuit is used to build selection window in selection window generator based on the delayed clock cycle of transmitted clock and the transmitted clock is compared with local clock to generate a selection signal in the SW(selection window). This MS gets rid of the restriction of metastability by choosing a rising edge or a falling edge of local clock according to the value of selection signal. The simulation results show that the proposed MS operates correctly for all phase differences between a transmitted clock and a local clock.

• The Transactions of the Korea Information Processing Society
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• v.5 no.3
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• pp.862-872
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• 1998

In this paper, we developed a delay test architecture and test procedure for clocked sequential circuit. In addition, we analyze the problems of conventional and previous method on delay test for clocked sequential circuit in IEEE 1149.1. This paper discusses several problems of Delay test on IEEE 1149.1 for clocked sequential circuit. Previous method has some problems of improper capture timing, of same pattern insertion, of increase of test time. We suggest a method called ARCH-S, is based on a clock counting technique to generate continuous clocks for clocked input of CUT. A 4-bit counter is selected for the circuit under test. The simulation results ascertain the aecurate operation and effectiveness of the proposed architecture.

• The Journal of Korean Institute of Communications and Information Sciences
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• v.35 no.12A
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• pp.1128-1135
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• 2010

A wireless positioning system using ultra-wideband (UWB) for indoor wireless positioning uses ranging data in order to accurately estimate location. Commonly, ranging uses time of arrival (TOA), time difference of arrival (TDOA) based on arrival time. The most fundamental issue in the ranging for wireless positioning is to obtain clock synchronization among the sensor nodes and to correct an error caused by the relative clock offset from each node. In this paper, we propose ranging and positioning technique using common clock in order to solve both clock synchronization and clock offset problems. To verify the performance of proposed, we simulated ranging and positioning in channel model introduced by IEEE 802.15.4a Task Group and then results show that location estimation is unaffected by clock offset.

• The KIPS Transactions:PartC
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• v.13C no.3 s.106
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• pp.303-310
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• 2006

This paper is to execute a study for characteristic analysis of synchronization clock and maximum network node number with various clock states, normal, SPT, LPT, in NG-SDH networks. Through the simulations, maximum network node numbers showed from 42 to 38 nodes in normal state. In SPT state, maximum network node numbers, when the last NE network applied to only SPT state, presented from 19 to 4 nodes, much less than normal state. Node numbers to meet specification in case of occurrence of SPT state in all NE networks decreased greatly. In LPT state, all maximum node numbers, when the last NE network applied to only LPT state, presented more than 50 nodes, and the results in case of occurrence of LPT state in all NE networks were also identified. However, node numbers to meet specification in case of LPT state in all DOTS networks were few large with difference between LPT and normal or SPT state.

• Electronics and Telecommunications Trends
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• v.13 no.1 s.49
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• pp.41-51
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• 1998

전역 클럭을 사용하는 동기 회로 설계 기술은 설계의 단순화 및 자동화가 용이하기 때문에 현재 많이 사용하는 설계 기술이다. 그러나 다양한 기능과 고성능을 필요로 하는 대규모 시스템이나 회로 설계에서는 전역 클럭 사용으로 인한 신호 지연, 전력 소모 등이 문제로 부각되면서 비동기 회로 설계 기술이 각광을 받고 있다. 비동기 회로 설계 기술은 1940년대에 개발된 기술이지만 설계 자체가 어렵고 면적 증가 등의 단점으로 제한된 분야에서 이용되었다. 현재 이러한 단점을 극복하기 위한 연구가 회로 설계, 검증, 동기/비동기 인터페이스, 그리고 저전력 회로 등의 분야에서 많이 진행되고 있다.

• Proceedings of the Korean Institute of Communication Sciences Conference
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• 1998.06a
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• pp.1184-1187
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• 1998