• Journal of the Institute of Electronics and Information Engineers
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• v.54 no.5
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• pp.24-32
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• 2017

In this paper, a low power 4th order delta-sigma modulator was designed with a high resolution of 12 bits or more for the biological signal processing. Using time-interleaving technique, 4th order delta-sigma modulator was designed with one operational amplifier. So power consumption can be reduced to 1/4 than a conventional structure. To operate stably in the big difference between the two capacitor for kT/C noise and chip size, the variable-stage amplifier was designed. In the first phase and second phase, the operational amplifier is operating in a 2-stage. In the third and fourth phase, the operational amplifier is operating in a 1-stage. This was significantly improved the stability of the modulator because the phase margin exists within 60~90deg. The proposed delta-sigma modulator is designed in a standard $0.18{\mu}m$ CMOS n-well 1 poly 6 Metal technology and dissipates the power of $354{\mu}W$ with supply voltage of 1.8V. The ENOB of 11.8bit and SNDR of 72.8dB at 250Hz input frequency and 256kHz sampling frequency. From measurement results FOM1 is calculated to 49.6pJ/step and FOM2 is calculated to 154.5dB.

• Journal of the Institute of Electronics Engineers of Korea SD
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• v.46 no.3
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• pp.26-31
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• 2009

A new LFSR based test compression scheme is proposed by reducing the maximum number of specified bits in the test cube set, smax, virtually. The performance of a conventional LFSR reseeding scheme highly depends on smax. In this paper, by using different clock frequencies between an LFSR and scan chains, and grouping the scan cells, we could reduce smax virtually. H the clock frequency which is slower than the clock frequency for the scan chain by n times is used for LFSR, successive n scan cells are filled with the same data; such that the number of specified bits can be reduced with an efficient grouping of scan cells. Since the efficiency of the proposed scheme depends on the grouping mechanism, a new graph-based scan cell grouping heuristic has been proposed. The simulation results on the largest ISCAS 89 benchmark circuit show that the proposed scheme requires less memory storage with significantly smaller area overhead compared to the previous test compression schemes.

• The Journal of Korean Institute of Communications and Information Sciences
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• v.22 no.9
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• pp.1916-1932
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• 1997

The synchronous stream cipher which require absoulte clock synchronization has the problem of synchronization loss by cycle slip. Synchronization loss makes the state which sender and receiver can't communicate with each other and it may break the receiving system. To lessen the risk, we usually use a continuous resynchronization method which achieve resynchronization at fixed timesteps by inserting synchronization pattern and session key. While we can get resynchronization effectively by continuous resynchroniation, there are some problems. In this paper, we proposed an adaptive resynchronization algorithm for cipher system using HDLC protocol. It is able to solve the problem of the continuous resynchronization. The proposed adaptive algorithm make resynchronization only in the case that the resynchronization is occurred by analyzing the address field of HDLC. It measures the receiving rate of theaddress field in the decision duration. Because it make resynchronization only when the receiving rate is greateer than the threshold value, it is able to solve the problems of continuous resynchronization method. When the proposed adaptive algorithm is applied to the synchronous stream cipher system in packet netork, it has addvance the result in R_e and D_e.

• Journal of the Institute of Electronics Engineers of Korea SD
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• v.39 no.11
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• pp.14-23
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• 2002

Two implementation methods for SOVA (Soft Output Viterbi Algorithm)of Turbo decoder are applied and verfied. The first method is the combination of a trace back (TB) logic for the survivor state and a double trace back logic for the weight value in two-step SOVA. This architecure of two-setp SOVA decoder allows important savings in area and high-speed processing compared with that of one-step SOVA decoding using register exchange (RE) or trace-back (TB) method. Second method is adjusting the reliability value with a scaling factor between 0.25 and 0.33 in order to compensate for the distortion for a rate 1/3 and 8-state SOVA decoder with a 256-bit frame size. The proposed schemes contributed to higher SNR performance by 2dB at the BER 10E-4 than that of SOVA decoder without a scaling factor. In order to verify the suggested schemes, the SOVA decoder is testd using Xillinx XCV 1000E FPGA, which runs at 33.6MHz of the maximum speed with 845 latencies and it features 175K gates in the case of 256-bit frame size.

• The KIPS Transactions:PartC
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• v.19C no.4
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• pp.239-246
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• 2012

The function of location estimation in WPAN has been studied and specified on the ultra wide band optionally. But the devices based on CSS(Chirp Spread Spectrum) specification has been used widely in the market because of its functionality, cheapness and support of development. As the CSS device uses 2.4GHz for a carrier frequency and the sampling frequency is lower than that of the UWB, the resolution of a timestamp is very coarse. Then actually the error of a measured distance is very large about 30cm~1m at 10 m depart. And the location error in ($10m{\times}10m$) environment is known as about 1m~2m. So for some applications which require more accurate location information, it is very natural and important to develop a sophisticated post processing algorithm after distance measurements. In this paper, we have studied extended Kalman filter with the frequency offsets of anchor nodes, and proposed a novel algorithm frequency offset compensated extended Kalman filter. The frequency offsets are composed with a variable as a common frequency offset and constants as individual frequency offsets. The proposed algorithm shows that the accurate location estimation, less than 10cm distance error, with CSS WPAN nodes is possible practically.

• Journal of the Korea Institute of Information Security & Cryptology
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• v.12 no.2
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• pp.21-34
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• 2002

In this paper we propos a new hardware architecture of modular exponentiation using a division chain method which has been proposed in (2). Modular exponentiation using the division chain is performed by receding an exponent E as a mixed form of multiplication and addition with divisors d=2 or $d=2^I +1$ and respective remainders r. This calculates the modular exponentiation in about $1.4log_2$E multiplications on average which is much less iterations than $2log_2$E of conventional Binary Method. We designed a linear systolic array multiplier with pipelining and used a horizontal projection on its data dependence graph. So, for k-bit key, two k-bit data frames can be inputted simultaneously and two modular multipliers, each consisting of k/2+3 PE(Processing Element)s, can operate in parallel to accomplish 100% throughput. We propose a new encoding scheme to represent divisors and remainders of the division chain to keep regularity of the data path. When it is synthesized to ASIC using Samsung 0.5 um CMOS standard cell library, the critical path delay is 4.24ns, and resulting performance is estimated to be abort 140 Kbps for a 1024-bit data frame at 200Mhz clock In decryption process, the speed can be enhanced to 560kbps by using CRT(Chinese Remainder Theorem). Futhermore, to satisfy real time requirements we can choose small public exponent E, such as 3,17 or $2^{16} +1$, in encryption and verification process. in which case the performance can reach 7.3Mbps.