• The Journal of Korean Institute of Communications and Information Sciences
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• v.32 no.10C
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• pp.1042-1050
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• 2007

This paper describes the system which automatically generates power-minimized embedded cores from MDL descriptions. An automatic generation system is constructed which generated embedded cores which consumes less power for application programs. From the usage information on pipeline stages for each instruction, the proposed system generates embedded cores with the capability of detecting/resolving pipeline hazards. The generated cores are configured such that the power consumption is minimized. The proposed system has been tested by generating HDL codes for ARM9, MIPS R3000 architectures. Experimental results show functional accuracy of the generated cores, and show that power reduction of $20%{\sim}40%$ has been observed for benchmark programs.

• The Journal of the Institute of Internet, Broadcasting and Communication
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• v.13 no.4
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• pp.171-177
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• 2013

Due to the demand for high speed 3D graphic rendering, video file format conversion, compression, encryption and decryption technologies, the importance of digital signal processor system is growing rapidly. In order to satisfy the real-time constraints, high performance digital signal processor is required. Therefore, as in general purpose computer systems, digital signal processor should be designed as multicore architecture as well. Using UTDSP benchmarks as input, the trace-driven simulation has been performed and analyzed for the 2 to 16-core digital signal processor architectures with the cores from simple RISC to in-order and out-of-order superscalar processors for the various window sizes, extensively.

• Land and Housing Review
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• v.14 no.1
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• pp.115-122
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• 2023

Modular construction is popular as a smart building system because it can shorten the construction period. This study proposed a precast concrete (PC) core system that can further shorten modular construction time. The system was developed and its structural performance was verified through computational analysis. The proposed PC core system is a complete PC construction method using dry bonding. The results of the study indicated that the proposed PC core system has structural stability and performance suitable for modular housing.

• Proceedings of the Korea Information Processing Society Conference
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• 2009.04a
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• pp.827-829
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• 2009

현재 멀티 코어 프로세서는 많은 서버에 적용되어 사용되고 있으며, 향후에는 하나의 프로세서 패키지에 포함될 코어의 개수는 계속해서 증가할 것이다. 그러나 현재 운영체제들은 멀티 코어 시스템을 멀티 프로세서 환경과 거의 동일하게 다루고 있으며 아직 멀티 코어 특성을 고려한 성능 최적화 시도는 미흡한 상태이다. 본 논문은 SMP와 NUMA 구조의 멀티 코어 프로세서 환경에서 통신 프로세스와 네트워크 인터럽트의 프로세서 친화도를 변화시키며 네트워크 처리율과 코어의 유휴 자원 양을 정량적으로 분석한다. 측정 결과 프로세서 친화도에 따라 통신 처리율은 크게 변하지 않지만 프로세서 자원의 요구량에는 크게 영향을 주는 것을 보인다. 또한 이러한 프로세서 자원의 영향은 멀티 코어 프로세서의 캐쉬 공유 구조 및 메모리 분산 구조와 밀접한 관계를 갖고 있음을 밝힌다.

• The Journal of Korean Institute of Communications and Information Sciences
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• v.30 no.6A
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• pp.526-534
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• 2005

This paper presents the structure and function of the system which automatically generates embedded processor cores using the SMDL. Accepting processor description in the SDML, the proposed system generates the processor core, consisting of the pipelined datapath and memory modules together with their control unit. The generated cores support muti-cycle instructions for proper handling of memory accesses, and resolve pipeline hazards encountered in the pipelined processors. Experimental results show the functional accuracy of the generated cores.

• Proceedings of the Korea Information Processing Society Conference
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• 2011.11a
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• pp.66-68
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• 2011

낮은 오버헤드를 갖는 실시간 스케줄링 알고리즘은 멀티코어 프로세서가 임베디드 시스템에서 사용되기 위한 가장 중요한 요소 중의 하나이다. 멀티코어 환경에서 스케줄링 오버헤드는 주로 메모리 성능을 저해시키는 코어간 태스크 이동에 의해 발생한다. 본 논문에서는 시스템 이용률 면에서 최적으로 알려진 Pfair 스케줄링 알고리즘을 스케줄링 시에 태스크의 CPU 코어 할당 방식에 대해 스케줄링 오버헤드를 측정하였다. 실험 결과 동일 코어 기반 태스크 할당 방식을 도입함으로 인해서 태스크 이동 횟수를 크게 줄일 수 있음을 보여주었다.

• KIISE Transactions on Computing Practices
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• v.23 no.1
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• pp.80-84
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• 2017

Existing operating systems experience scalability issues as the number of cores increases. The network I/O performance on manycore systems is faced with the major limiting factors of cache consistency costs and locking overheads. Legacy methods resolve this issue include the new microkernel-like operating system or modification of existing kernels; however, these solutions are not fully application transparent. In this study, we proposed a library that improves the network performance by separating system call context from user context and by applying the core affinity without any kernel and application modifications. Experiment results showed that our implementation can improve the network throughput of Apache by up to 30%.

• KIPS Transactions on Computer and Communication Systems
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• v.4 no.5
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• pp.153-160
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• 2015

The effectiveness of multicores depends on how well a scheduler can assign tasks onto the cores efficiently. In a heterogeneous multicore platform, the execution time of an application depends on which core it executes on. That is to say, the effectiveness of task assignment is one of the important components for a multicore systems' performance. This work proposes a load scheduling technique that analyzes execution time of each task by profiling. The profiling result provides a basic information to predict which task-to-core mapping is likely to provide the best performance. By using such information, the proposed technique is about 26% performance gain.

• Journal of KIISE
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• v.43 no.7
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• pp.736-743
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• 2016

Several studies have reported the impact of core affinity on the network I/O performance of multi-core systems. As the network bandwidth increases significantly, it becomes more important to determine the effective core affinity. Although a framework for dynamic core affinity that considers both network and disk I/O has been suggested, the multiple queues provided by high-speed I/O devices are not properly supported. In this paper, we extend the existing framework of dynamic core affinity to efficiently support the multiple queues of high-speed I/O devices, such as 40 Gigabit Ethernet and NVM Express. Our experimental results show that the extended framework can improve the HDFS file upload throughput by up to 32%, and can provide improved scalability in terms of the number of cores. In addition, we analyze the impact of the assignment policy of multiple I/O queues across a number of cores.

• Proceedings of the Korea Information Processing Society Conference
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• 2022.11a
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• pp.2-4
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• 2022

매니코어 CPU 시스템에서의 병렬 I/O 는 현재의 리눅스 시스템의 LRU 관리 방법의 한계로 확장성에 문제를 가지고 있다. 본 연구에서는 이 문제를 해결했던 하기 위한 개선된 FinerLRU 를 제안한다. LRU 락을 최대 코어 개수만큼 증가시키고 세분화된 Lock 관리를 통해 버퍼 캐시를 사용하는 파일 시스템의 병렬 I/O 성능을 향상시킨다. 리눅스 5.18.11 에 제안한 방법을 구현하였으며, 64 개의 물리적 코어와 256 개의 논리적 코어를 가지는 Intel Knights Landing 프로세서를 이용한 실험을 통해 두 배 가량의 성능 향상을 얻을 수 있음을 확인하였다.