• Proceedings of the Korea Information Processing Society Conference
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• 2004.05a
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• pp.519-522
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• 2004

자바는 현재 가장 널리 사용되는 범용 프로그래밍 언어중 하나로 컴파일러에 의해 중간언어인 바이트코드로 변환되며 JVM(Java Virtual Machine)에 의해 실행되는 플랫폼 독립적인 언어이다. SIL(Standard Intermediate Language)은 Microsoft사의 .NET 언어와 SUN사의 Java 언어 등을 모두 수용할 수 있는 임베디드 시스템을 위한 중간언어로 가상기계인 EVM(Embedded Virtual Machine)에서 실행된다. 본 논문에서는 자바 프로그램을 컴파일하여 생성된 클래스 파일에서 Oolong 코드를 추출하고 추출된 Oolong 코드를 EVM의 SIL 코드로 변환하여 자바로 구현된 프로그램이 EVM에서 실행되도록 하는 Bytecode-to-SIL 번역기 시스템을 구현하였다. 그리고 본 번역기 시스템을 다른 플랫폼에 용이하게 설치하기 위한 재목적성(retargetability)을 위해 단일패스(one-pass)을 사용하는 기존의 번역기들과 달리 AST를 이용한 컴파일러 기법을 사용하여 AST가 가지고 있는 정보에 대해 최적화 작업을 수행하여 보다 효과적인 코드 변환을 할 수 있도록 설계하였다.

• Proceedings of the Korea Information Processing Society Conference
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• 2020.05a
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• pp.375-376
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• 2020

높은 사양이 필요한 하드웨어 기반의 모바일 및 IoT 임베디드 시스템은 저전력과 성능에 중요한 이슈를 갖고 있다. 이는 전력 소비로 발열량 증가 및 기기의 수명 단축 문제가 발생된다. 이러한 환경에서 소프트웨어도 제한된 전력, 메모리 등에서 안정적인 동작을 수행해야 하므로 디바이스의 소비전략이 증가한다. 이를 해결하고자, 코드 관점에서 전력 소모 최소화를 통한 소프트웨어 성능 개선 가시화 방법을 제안한다. 이는 코드 가시화를 통해 복잡한 모듈을 식별하고, 저전력 코드 패턴을 적용하여 소프트웨어 성능을 개선한다. 이런 코드로 소비전력을 감소 및 성능을 개선함으로써 코드의 품질을 최적화 할 수 있다.

• Proceedings of the Korea Information Processing Society Conference
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• 2004.11a
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• pp.429-432
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• 2004

자바 언어는 객체지향 언어이며 효율적인 애플리케이션을 개발하기 위해 설계되었다. 특히 다양한 개발 환경과 이식성에 맞는 언어로써 각광을 받고 있다. 하지만 자바 언어로 애플리케이션을 개발하면 다른 언어로 작성하는 것 보다 실행이 느리다는 단점을 가지고 있다. 이러한 자바 실행 속도를 극복하기 위해 많은 연구가 되고 있는데, 그 중에서도 JIT방식과 네이티브 코드로 변환 방식이 있다. 본 논문은 스택기반의 자바 바이트코드에서 3-주소 형태로 변환하여 최적화하는 CTOC중에서 바이트코드에서 3-주소 형태 즉 CTOC-T의 중간 표현인 CTOC-B를 설계하려 한다. CTOC-B는 스택기반의 중간표현으로써 자바 바이트코드보다 코드의 변환과 분석이 용이하게 만든 형태의 표현이다. 본 논문에서는 자바 바이트코드에서 스택기반 중간코드인 CTOC-B 코드로의 효율적인 변환기를 설계하며, CTOC-B의 특징을 분석해 본다.

• KIISE Transactions on Computing Practices
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• v.23 no.3
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• pp.188-193
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• 2017

In this paper, we propose automatic OpenCL optimization techniques that offer the best performance for image processing programs on any hardware system. Developers should seek a proper way of parallelization and an appropriate work-group size for the architecture of target compute devices to achieve the best performance. However, testing potential devices to find them is both time-consuming and costly. Our techniques automatically set up hardware-optimized parallelization and find a suitable work-group size for the target device. Furthermore, using OpenCL does not always provide better performance in image processing. Hence, we also propose a way to automatically search for a threshold image size to allow image processing programs to decide whether or not to use OpenCL. Our findings demonstrate that out techniques improve the image processing performance significantly.

• The Journal of the Korea Contents Association
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• v.6 no.2
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• pp.117-126
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• 2006

Although the Java bytecode has numerous advantages, there are also shortcomings such as slow execution speed and difficulty in analysis. In order to overcome such disadvantages, bytecode analysis and optimization must be performed. First control flow of the bytecode should be analyzed, after which information is required regarding where the variables are defined and used to conduct data flow analysis and optimization. There may be cases where variables with an identical name contain different values at a different location during the execution according to the value assigned to a variable in each location. Therefore, in order to statically determine the value and type, the variables must be separated according to allocation. In order to do so, the variables can be expressed using a static single assignment form. After the transformation into a static single assignment form, the type information of each node expressed by each variable and expression must be configured to perform static analysis and optimization. Based on the basic type information, this paper proposes a method for finding related equivalent nodes, setting the nodes with strongly connection components and efficiently assigning each node the type.

• Journal of Intelligence and Information Systems
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• v.6 no.2
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• pp.41-47
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• 2000

Ideograph is a truly unifies data and procedural dependencies. Ideograph can be used to assist various program optimization, such as common expression elimination, code motion, constant folding etc. In this paper, we propose an improved representation of the data and control flow dependencies information for the efficient program execution. In pursuing this goal, we propose a model and in particularly implement a dependency information extractor and information table, which contains data and control flow information per a basic block And then we design and implementation of the optimized abstract syntax tree using Ideograph which has a control flow information and data flow information for source program.

• The tire
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• s.135
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• pp.19-23
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• 1988

• The Journal of Korean Institute of Communications and Information Sciences
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• v.36 no.1B
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• pp.71-79
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• 2011

This paper proposes a compiled-code simulator generation system based-on machine description language for efficient design space exploration in designing an embedded system optimized for a specific application. The proposed system generates a compiled-code simulator which maintains the functional accuracy of an event-driven simulator by determining instruction fetch and decoding processes statically. Generated simulator takes instruction-level and cycle-level simulation for estimating performances in embedded core. To show the efficiency of the constructed compiled-code simulator generator, architecture exploration had been performed for the JPEG encoder application. Starting with MIPS R3000 processor for one embedded core, the proposed system can produce the core showing optimized execution time for the application programming. In this process, a huge amount of simulation time has been used. Cycle-level compiled-code simulator has the functional accuracy and shows performance improvement by 21.7% in terms of simulation speed on the average when compared with an event-driven simulator.

• Journal of the Korea Institute of Information and Communication Engineering
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• v.22 no.7
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• pp.993-1000
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• 2018

This paper proposes a low-dropout voltage regulator(LDO) using self-cascode structure. The self-cascode structure was optimized by adjusting the channel length of the source-side MOSFET and applying a forward voltage to the body of the drain-side MOSFET. The self-cascode of the input differential stage of the error amplifier is optimized to give higher transconductance, but the self-cascode of the output stage is optimized to give higher output resistance, The proposed LDO using self-cascode structure was designed by a $0.18{\mu}m$ CMOS technology and simulated using SPECTRE. The load regulation of the proposed LDO regulator was 0.03V/A, whereas that of the conventional LDO was 0.29V/A. The line regulation of the proposed LDO regulator was 2.23mV/V, which is approximately three times improvement compared to that of the conventional LDO. The transient response of the proposed LDO regulator was 625ns, which is 346ns faster than that of the conventional LDO.

• Journal of the Korea Society of Computer and Information
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• v.11 no.4 s.42
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• pp.87-96
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• 2006

Although bytecode has many good features, it has slow execution speed and it is not an ideal representation for program analysis or optimization. For analysises and optimizations. bytecode must be translated to a Static Single Assignment Form(SSA Form) But when bytecode is translated a SSA Form it has lost type informations of son variables. For resolving these problem in this paper, we create extended control flow graph on bytecode. Also we convert the control flow graph to SSA Form for static analysis. Calculation about many informations such as dominator, immediate dominator. dominance frontier. ${\phi}$-Function. renaming are required to convert to SSA Form. To obtain appropriate type for generated SSA Form, we proceed the followings. First. we construct call graph and derivation graph of classes. And the we collect information associated with each node. After finding equivalence nodes and constructing Strongly Connected Component based on the collected informations. we assign type to each node.