• Journal of the Korea Academia-Industrial cooperation Society
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• v.10 no.12
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• pp.3626-3631
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• 2009

This study has provided some of the first experimental results of NMOSFET hot-carrier degradation for the analog circuit application. After hot-carrier stress under the whole range of gate voltage, the degradation of NMOSFET characteristics is measured in saturation region. In addition to interface states, the evidences of hole and electron traps are found near drain depending on the biased gate voltage, which is believed to the cause for the variation of the transconductance($g_m$) and the output conductance($g_{ds}$). And it is found that hole trap is a dominant mechanism of device degradation in a low-gate voltage saturation region, The parameter degradation is sensitive to the channel length of devices. As the channel length is shortened, the influence of hole trap on the channel conductance is increased. Because the magnitude of $g_m$ and $g_{ds}$ are increased or decreased depending on analog operation conditions and analog device structures, careful transistor design including the level of the biased gate voltage and the channel length is therefore required for optimal voltage gain ($A_V=g_m/g_{ds}$) in analog circuit.

• The Journal of Korean Institute of Communications and Information Sciences
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• v.24 no.10A
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• pp.1579-1587
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• 1999

Bias-dependent noise models of $0.2\mu\textrm{m}$ gate length P-HEMT's which are scalable with gate width are proposed. To predict S-parameters of the P-HEMT's the intrinsic parameters except for $\tau$ subtracted the offsets introduced in this paper are normalized to the gate width and then scaled. The small-signal model parameters are expressed as fitting functions of the drain current to $\textrm{I}_{dss}$ ratio and gate width. In addition, to estimate accurately noise parameters the noise temperature $\textrm{T}_{g}$ of the intrinsic resistance, the equivalent noise conductance $\textrm{G}_{ni}$ of the gate current noise source, and the equivalent noise conductance $\textrm{G}_{no}$ of the drain current noise source are adopted as the noise model parameters. The extracted values of $\textrm{T}_{g}$ are nearly independent of drain current and gate width and their average is around the ambient temperature. The extracted values of $\textrm{G}_{ni}$ are small enough to be neglected to the circuit characteristics. From the comparison of the noise model with only $\textrm{G}_{no}$ and that having $\textrm{T}_{g}$, $\textrm{G}_{ni}$ and $\textrm{G}_{no}$ to the measured data it is fund that even the former model is in good agreement with the measured noise parameters. Thus, from a practical point of view the noise model having only the drain current noise source is confirmed as a scalable bias-dependent model.

• The Journal of the Institute of Internet, Broadcasting and Communication
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• v.15 no.5
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• pp.201-206
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• 2015

A new electronically stopband tunable filter is proposed with three-input single-output using Operational Transconductance Amplifier (OTA) in this paper. The proposed filter provides band pass, low pass and high pass multifunctional responses. Centre frequency ($f_c$) and quality factor (Q) of the realized filters could independently tuned without disturbing each other. Various network sensitivity and non-ideal characteristic analysis are done to check the sensitivity and parasitic effect of different circuit parameters. The CMOS realization of filter is done with 1.8V-0.18um process parameters and HSPICE simulation results are presented to assert the presented theory.

• Journal of Advanced Navigation Technology
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• v.3 no.2
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• pp.174-184
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• 1999

In this paper, the equations which can be used to calculate the minimum series stabilizing resistance and /or the minimum parallel stabilizing conductance using the S parameters of an active device has been derived. The equation derived can be used to design a stabilizing circuit of minimum loss of a maximum available gain of a device when the circuit is adopted. For the case of KGF1254B which can be used at 1.9 GHz, the circuit proposed in this paper reduce the maximum available gain by 1 dB, while conventional simple resistor circuit reduce it by 5.2 dB.

• Journal of Korea Multimedia Society
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• v.7 no.11
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• pp.1515-1520
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• 2004

In this paper, a new continuous-time bandpass active filter for lour-voltage applications is proposed. The active filter is composed of the CMOS complementary cascode circuit which can increase trans-conductance of an active element. These results are verified through the 0.25$\mu\textrm{m}$ CMOS n-well parameter hspice simulation. As a result, the gain and the unity gain frequency is 42dB and 200MHz respectively in the integrator. Additionally, center frequency of the bandpass active filter is 747kHz. And also bandwidth of the filter is 649kHz on 2V supply voltage.

• Journal of the Korea Institute of Information and Communication Engineering
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• v.16 no.11
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• pp.2480-2486
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• 2012

The design of low voltage LC-VCO(LC Voltage Controlled Oscillator) has been presented to optimize the phase noise and power consumption for the block of frequency synthesis to satisfy WCDMA system specification in this paper. The parameters for minimum phase noise has been obtained in the region of design, using the lines of the tuning range and the excess gain in the plane of the inductance and the transconductance of MOS transistor to compensate the loss of LC-tank. As a result of simulation, the phase noise characteristics is -113dBc/Hz for offset of 1MHz. The optimum designed LC-VCO has been fabricated using the process of 0.25um CMOS. As a result of measurement for fabricated chip, the phase noise characteristics is -116dBc/Hz for offset of 1MHz. The power consumption is 15mW, and Kvco is 370MHz/V.

• Journal of the Institute of Electronics Engineers of Korea SD
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• v.45 no.9
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• pp.21-25
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• 2008

In this study, to maximize RF performance of MOSFETs, $f_T$ and $f_{max}$ dependent data on $W_u$ are measured and newly analyzed by extracting small-signal model parameters. From the physical analysis results, it is found that a peak value of $f_T$ is generated by $W_u$-independent parasitic gate-bulk capacitance at narrow $W_u$ and the wide width effect of reducing the increasing rate of transconductance at wide $W_u$. In addition, it is revealed that a maximum value of $f_{max}$ is caused by the non-quasi-static effect that the gate resistance is greatly reduced at narrow $W_u$ and becomes constant at wide $W_u$.

• Journal of the Institute of Electronics Engineers of Korea SD
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• v.40 no.9
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• pp.644-650
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• 2003

In this paper, we have studied characteristics of PHEMT's fabricated by two difference types of gate recess for improving performance of the device in millimeter wave applications. PHEMT's were fabricated using wide and narrow recesses. Maximum transconductance(g$_{m}$) of PHEMT's using the wide recess was 332.7 mS/mm, and that of PHEMT's using narrow recess was 504.6 mS/mm. From small signal performance measurements, cutoff frequency(f$_{T}$) and maximum stable oscillation frequency(f$_{max}$) of PHEMT's using wide recess were 113 GHz and 172 GHz, respectively. f$_{T}$ and f$_{max}$ of PHEMT using narrow recess were 101 GHz and 142 GHz, respectively. The measured data of the fabricated PHEMTs' were carefully studied and analyzed.d.tudied and analyzed.

• Journal of the Korea Institute of Information and Communication Engineering
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• v.12 no.9
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• pp.1615-1622
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• 2008

We have fabricated the poly-silicon thin film transistor(TFT) which has the LDD-region with graded spacer. The devices of n-channel poly-si TFT's hydrogenated by $H_2$ and $H_2$/plasma processes were fabricated for the devices reliability. We have biased the devices under the gate voltage stress conditions of maximum leakage current. The parametric characteristics caused by gate voltage stress conditions in hydrogenated devices are investigated by measuring/analyzing the drain current, leakage current, threshold voltage($V_{th}$), sub-threshold slope(S) and transconductance($G_m$) values. As a analyzed results of characteristics parameters, the degradation characteristics in hydrogenated n-channel polysilicon TFT's are mainly caused by the enhancement of dangling bonds at the poly-Si/$SiO_2$ interface and the poly-Si grain boundary due to dissolution of Si-H bonds. The structure of novel proposed poly-Si TFT's are the simplicities of the fabrication process steps and the decrease of leakage current by reduced lateral electric field near the drain region.

• Proceedings of the Korean Institute of Information and Commucation Sciences Conference
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• 2008.05a
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• pp.105-110
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• 2008

We have proposed a new structure of poly-silicon thin film transistor(TFT) which was fabricated the LDD region using doping oxide with graded spacer by etching shape retio. The devices of n-channel poly-si TFT's hydrogenated by $H_2$ and $HT_2$/plasma processes are fabricated for the devices reliability. We have biased the devices under the gate voltage stress conditions of maximum leakage current. The parametric characteristics caused by gate voltage stress conditions in hydrogenated devices are investigated by measuring /analyzing the drain current, leakage current, threshold voltage($V_{th}$), sub-threshold slope(S) and transconductance($G_m$) values. As a analyzed results of characteristics parameters, the degradation characteristics in hydrogenated n-channel polysilicon TFT's are mainly caused by the enhancement of dangling bonds at the poly-Si/$SiO_2$ interface and the poly-Si Brain boundary due to dissolution of Si-H bonds. The structure of novel proposed poly-Si TFT's are the simplity of the fabrication process steps and the decrease of leakage current by reduced lateral electric field near the drain region.