• Proceedings of the Korea Society for Simulation Conference
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• 1999.10a
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• pp.138-143
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• 1999

초고속 정보통신망을 비롯한 인프라의 구축이 확대되면서 다양한 종류의 정보 서비스들이 활성화되고 있다. 최근 인터넷의 사용자 수가 크게 증가함에 따라 웹 서버에 걸리는 부하와 통신망의 트래픽이 급증하고 있으며, 이들은 응답시간을 지연시키는 주요 요인이 되고 있다. 이러한 문제를 해결하기 위하여 액세스 빈도가 높은 정보는 클라이언트에 가까이 위치한 프록시 서버에 캐슁함으로써 웹서버의 병목현상을 완화시키고, 통신망의 트래픽을 줄이며, 서비스 응답시간을 줄일 수 있다. 또한 여러 프록시 캐쉬들에 저장된 정보들을 클라이언트들이 공유함으로써 인터넷 성능을 보다 향상시킬수 있다. 본 논문에서는 실제 웹 트레이스를 이용한 시뮬레이션을 이용하여, 3-레벨 4진 트리(3-level 4-ary tree) 구조의 계층적 프록시 캐슁 환경에서 캐쉬 교체 정책에 따른 캐쉬 적중률의 변화를 분석하고, 인터넷 서비스 향상을 위한 최적의 교체방식을 제안한다.

• Journal of KIISE
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• v.41 no.11
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• pp.871-877
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• 2014

Cache replacement algorithms have been developed in order to reduce miss counts. In modern processors, the performance gap between the processor and main memory has been increasing, creating a more important role for cache replacement policies. The Least Recently Used (LRU) policy is one of the most common policies used in modern processors. However, recent research has shown that the performance gap between the LRU and the theoretical optimal replacement algorithm (OPT) is large. Although LRU replacement has been proven to be adequate over and over again, the OPT/LRU performance gap is continuously widening as the cache associativity becomes large. In this study, we observed that there is a potential chance to improve cache performance based on existing LRU mechanisms. We propose a method that enhances the performance of the LRU replacement algorithm based on the access proportion among the lines in a cache set during a period of two successive replacement actions that make the final replacement action. Our experimental results reveals that the proposed method reduced the average miss rate of the baseline 512KB L2 cache by 15 percent when compared to conventional LRU. In addition, the performance of the processor that applied our proposed cache replacement policy improved by 4.7 percent over LRU, on average.

• Journal of the Korea Society of Computer and Information
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• v.18 no.11
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• pp.1-12
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• 2013

In multi-core processors, Last Level Cache(LLC) can reduce the speed gap between the memory and the core. For this reason, LLC has big impact on the performance of processors. LLC is composed of shared cache and private cache. In computer architecture community, most researchers have mainly focused on the management techniques for shared cache, while management techniques for private cache have not been widely researched. In conventional private LLC, memory is statically assigned to each core, resulting in serious performance degradation when the workloads are not fairly distributed. To overcome this problem, this paper proposes the replacement policy for managing private cache of LLC efficiently. As proposed core-aware cache replacement policy can reconfigure LLC dynamically, hit rate of LLC is increases drastically. Moreover, proposed policy uses 2-bit saturating counters to improve the performance. According to our simulation results, the proposed method can improve hit rates by 9.23% and reduce the access time by 12.85% compared to the conventional method.

• Journal of KIISE:Computer Systems and Theory
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• v.30 no.7_8
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• pp.426-433
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• 2003

Management policies of Web Proxy Cache, for the QoS of Web users, are mainly focused on the page replacement and the data consistency policy. But the two subjects have been studied independently to each other regardless of its possibility of cooperation. In this paper, we introduce the performance improvement obtained by adapting the characteristic of LMF used in data consistency policy to LRU, thus taking the better performance synergy as a result of complementary cooperation. Various policies for the management of Web Proxy Cache are in progress, this study can be a way of performance guide to increase cache hit ratio and reduce the transmission overhead of Web Server.

• Journal of the Institute of Electronics Engineers of Korea SD
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• v.46 no.1
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• pp.68-75
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• 2009

As the recent performance of microprocessor is improving quickly, the necessity of cache is growing because of the increase of the access time of main memory. Every block of direct-mapped cache maps to one cache line. Although the mapping rule is simple, if different blocks map to one cache line, the miss ratio will be higher than the set-associative cache due to conflicts. In this paper, for the improvement of the direct-mapped cache of OpenRISC, 4-way set-associative cache is proposed. Four blocks of the main memory of the proposed cache map to one cache line so that the miss ratio is less than the direct-mapped cache. Pseudo-LRU Policy, which is one of the Line Replacement Policies, is used for decreasing the number of bits that store LRU value. The OpenRISC core including the 4-way set-associative cache was verified with FPGA emulation. As the result of performance measurement using test program, the performance of the OpenRISC core including the 4-way set-associative cache is higher than the previous one by 50% and the decrease of miss ratio is more than 15%.

• Journal of the Korea Institute of Information and Communication Engineering
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• v.14 no.2
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• pp.453-461
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• 2010

This paper presents a branch prediction algorithm and a 4-way set-associative cache for performance improvement of embedded RISC core and a clock-gating algorithm using ODC (Observability Don't Care) operation to improve the power consumption of the core. The branch prediction algorithm has a structure using BTB(Branch Target Buffer) and 4-way set associative cache has lower miss rate than direct-mapped cache. Pseudo-LRU Policy, which is one of the Line Replacement Policies, is used for decreasing the number of bits that store LRU value. The clock gating algorithm reduces dynamic power consumption. As a result of estimation of performance and dynamic power, the performance of the OpenRISC core applied the proposed architecture is improved about 29% and dynamic power of the core using Chartered $0.18{\mu}m$ technology library is reduced by 16%.

• Journal of KIISE:Computing Practices and Letters
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• v.10 no.3
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• pp.282-291
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• 2004

There has been many researches in TopicMap and RDF which are approach to handle data efficiently with metadata. However, No researches has been performed to service and implement except for presentation and description. In this paper, We suggest the caching mechanism to support an efficient access of knowledgemap and practical knowledgemap service with implementation of TopicMap system. First, We propose a method to navigate Knowledgemap efficiently that includes advantage of former methods. Then, To transmit TopicMap efficiently, We suggest caching mechanism for knowledgemap. This method is that user will be able to navigate knowledgemap efficiently in the viewpoint of human, not application. Therefor the mechanism doesn't cash topics by logical or physical locality but clustering by information and characteristic value of TopicMap. Lastly, we suggest replace mechanism by using graph structure of TopicMap for efficiency of transmission.

• Proceedings of the Korea Society for Industrial Systems Conference
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• 1998.10a
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• pp.815-825
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• 1998

이 논문은 객체지향 데이터베이스 관리시스템에서 캐쉬의 효율성을 개선하기 위한 일련의 기술이다. 제안된 방법은 두단계로 나누어진다. 첫 번째 단계에서는 다양한 질의에 대한 디스크 접근 빈도수가 방식에 대해 분석하였으며 , 두 번째 단계에서는 첫 번째 단계의 분석된 결과를 바탕으로 접근 빈도가 높은 페이지를 선채취하였다. 이 연구에서는 기존의 선채취 기법에 쓰기 정보를 감안한 방법을 추가하여 다양한 선채취 캐슁기법을 제안한다. 기본적으로 이 방법은 정보변경이 일어난 페이지에 대해 쓰기비용이 발생되므로 교체를 지연한다. 실험결과는 일관되게 현존하는 알고리즘 보다 나은 결과를 보여준다.

• Journal of KIISE:Databases
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• v.35 no.6
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• pp.469-480
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• 2008

A shared disk (SD) cluster couples multiple nodes for high performance transaction processing, and all the coupled nodes share a common database at the disk level. To reduce the number of disk accesses, each node caches database pages in its memory buffer. Since a particular page may be cached simultaneously in different nodes, cache consistency should be maintained to ensure that nodes can always access the most recent version of database pages. Most cache consistency schemes proposed in the SD cluster adopted LRU as a buffer replacement algorithm. In this paper, we first present four buffer replacement algorithms that consider the characteristics of the SD cluster. Then we compare the performance of the buffer replacement algorithms. We perform the experiments on a variety of cluster configurations and database workloads. The experiment results show that the proposed algorithms achieve performance improvement up to 5 times of LRU algorithm.