• Applied Chemistry for Engineering
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• v.20 no.6
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• pp.571-580
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• 2009

Biochip sensing technologies offering in-situ, fast and real-time measurements in addition to portability can be powerfully utilized in a wide spectrum of research areas including environmental science, food science, medical diagnostics and drug development. In this article, we introduce current research trends and economic aspects of the development of various optical biochip technologies for the analysis of organophosphorus/carbamate pesticides in environmental samples, which is of global importance with serious consequences for both current and future generations. In particular, we will highlight recent efforts made in the creation of highly sensitive and selective optical biochip sensors in conjunction with nanobiotechnologies and microfabrication for the rapid detection of organophosphorus/carbamate pesticides.

• Journal of Biomedical Engineering Research
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• v.18 no.4
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• pp.467-476
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• 1997

This paper presents a designing of a digital hearing aid processor (DHAP) chip being operated by a dedicated DSP core. The DHAP for hearing aid devices must be feasible within a size and power consumption required. Furthermore, it should be able to compensate for wide range of hearing losses and allow sufficient flexibility for the algorithm development. In this paper, a programmable 16-bit fixed-point DSP core is employed thor the designing of the DHAP. The designed DHAP performs a nonlinear loudness correction of 8 frequency bands based on audiometric measurements of impaired subjects. By employing a programmable DSP, the DHAP provides all the flexibility needed to implement audiological algorithms. In addition, the chip has low-power feature and $5, 500\times5000$$\mu$$m^2$ dimensions that fit for wearable hearing aids.

• Journal of the Korea Institute of Information and Communication Engineering
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• v.25 no.2
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• pp.259-266
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• 2021

USB bus not only works with convenience but also transmits data fast and becomes a standard peripheral interface between FPGA development board and personal computer. In this paper FPGA verification system with slave FIFO interface for Cypress FX3 USB 3 bridge chip was implemented. The designed slave FIFO interface consists of host interface module based on FIFO structure, master bus controller and command decoder and supports streaming communication interface for FX3 bridge chip and memory-mapped input and output interface for user design circuit. The ZestSC3 board with Cypress FX3 USB 3 bridge chip and Xilinx Artix FPGA(XC7A35T-1C5G3241) was used to implement FPGA verification system. It was verified that the FPGA verification system for user design circuit operated correctly under various clock frequencies using GUI software developed by visual C# and C++ DLL. The designed slave FIFO interface for FPGA verification system has modular structure and can be applicable to the different user designs with memory-mapped I/O interface.

• Journal of IKEEE
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• v.11 no.4
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• pp.145-151
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• 2007

In this work, small-size, high-performance solenoid-type RF chip inductors utilizing a low-loss ${Al_2}{O_3}$ core material were investigated. The size of the chip inductors fabricated in this work were $0.86{\times}0.46{\times}0.45m^3$, $1.5{\times}1.0{\times}0.7m^3$, $2.1{\times}1.5{\times}1.0m^3$, and $2.4{\times}2.0{\times}1.4m^3$ and copper (Cu) wire with $27{\sim}40{\mu}m$ diameter was used as the coils. High frequency characteristics of the inductance, quality factor, and impedance of developed inductors were measured using an RF Impedance/Material Analyzer (HP4291B with HP16193A test fixture). It was observed that the developed inductors with the number of turns of 7 have the inductance of 13 to 100nH and exhibit the self-resonant frequency (SRF) of 6.4 to 1.1GHz. The SRF of inductors decreases with increasing the inductance and the inductors have the quality factor of 50 to 80 in the frequency range of 300MHz to 1.3GHz. In this study, small-size solenoid-type RF chip inductors with high inductance and high quality factor were fabricated successfully.

• Transactions of the Korean Society of Mechanical Engineers
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• v.16 no.6
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• pp.1121-1140
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• 1992

In metal cutting the shape of generated chip varies according to cutting conditions, characteristics of workpiece and geometry of cutting tool. The best surface roughness of machined workpiece is obtained when generating flow type contrinuous chip. If the generated chip is not broken, that is not only tangled workpiece and cutting tool, but also may give damage on the machined surface of workpiece or danger for a operator. The flow type continuous chip may bring the low productivity in high speed any heavy cutting, automatic machining process and non-human factory. There are two type of chip break process ; controlling cutting condition and using chip breaker. In present study we carried out the experiment on new type chip breaker compared with conventional type and proved the efficiency of a new type and showed the chip break condition to be applied in actual metal cutting. In the experiment SM 20 C as a workpiece material and WC as a tool material were used and cutting speed of 30-150m/min, feed of 0.071-0.210mm/rev and depth of cut of 1mm were applied as cutting condition. The results of the experiment are as follows : (1) The mechanism of chip curl can be explained more clearly by plastic flow of workpiece material and moment of shearing force. (2) The most effective radius of curled chip and flat distance from cutting edge is 2.0-2.5mm and 1.5mm in both types. (3) The effective inclination angle of chip break surface and side cutting edge angle are 30.deg.- 45.deg. and 20.deg. in conventional type, while the radius of arc surface, lower arc angle A, upper arc angle B and side cutting edge angle are 3mm, 20.deg.- 45.deg., 0.deg.- 45.deg. and 10.deg.- 20.deg. in new type. (4) The probability to be obtained 100% chip breaking ratio is much higher in new type than in conventional type.

• Journal of the Korean Society of Surveying, Geodesy, Photogrammetry and Cartography
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• v.32 no.4_1
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• pp.319-326
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• 2014

The accurate geo-referencing processes that apply ground control points is prerequisite for effective end use of HRSI (High-resolution satellite imagery). Since the conventional control point acquisition by human operator takes long time, demands for the automated matching to existing reference data has been increasing its popularity. Among many options of reference data, the airborne LiDAR (Light Detection And Ranging) data shows high potential due to its high spatial resolution and vertical accuracy. Additionally, it is in the form of 3-dimensional point cloud free from the relief displacement. Recently, a new matching method between LiDAR data and HRSI was proposed that is based on the image projection of whole LiDAR data into HRSI domain, however, importing and processing the large amount of LiDAR data considered as time-consuming. Therefore, we wmotivated to ere propose a local LiDAR chip generation for the HRSI geo-referencing. In the procedure, a LiDAR point cloud was rasterized into an ortho image with the digital elevation model. After then, we selected local areas, which of containing meaningful amount of edge information to create LiDAR chips of small data size. We tested the LiDAR chips for fully-automated geo-referencing with Kompsat-2 and Kompsat-3 data. Finally, the experimental results showed one-pixel level of mean accuracy.

• The Journal of Korean Institute of Electromagnetic Engineering and Science
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• v.16 no.2 s.93
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• pp.204-210
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• 2005

In this paper, we are proposed the antennas for RFID tag operated at UHF band which are inserted ground plane easy to mount the RFTD chips at the antenna surfaces. In order to implemented antenna for RFID tag which the size is same as conventional name card, the structure of the antenna is meander type, matching method for improvement characteristics of the antenna use T matching method, ground plane is inserted at the antenna substrate fer mounting RFID chips. The substrate size of implementation is $100\times60\;mm^2$ and the FR4 substrate is used. Results of the experiment, the center frequency of the implemented antenna is 427 MHz, -10 dB return loss bandwidth is 8 MHz, maximum return loss is 21 dB, the radiation pattern is omnidirectional. From these results, we are conformed application for UHF RFID tag antenna.

• The Journal of Korean Institute of Electromagnetic Engineering and Science
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• v.11 no.1
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• pp.55-62
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• 2000

In this paper, cellularphone antenna was designed to be capable of being mounted on the circuit-board with co-planar feeding method. The designed antenna is fabricated by the following procedure : make the multi-layered dielectric ceramic($\varepsilon_{\tau}$=23) hexahedron($7.5mm\times4.5mm\times0.4mm$) and then produce λ/4 monopole radiation element with helical structure on the surface of the hexahedron. The results are as followings : Returnloss 27.36 dB, -10 dB bandwidth 76 MHz(3.97 %), H-plane average gain -9.43 dBd.

• The Journal of Korean Institute of Electromagnetic Engineering and Science
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• v.16 no.8 s.99
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• pp.797-802
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• 2005

In this paper, we design a UHF band RFID tag antenna which is conjugate matched to an impedance of a chip and also mountable on conductive materials. The proposed tag antenna is very compact($50{\times}30{\times}4mm$) with a modified PIFA shape. The proposed tag antenna has an advantage of easy matching to various chip input impedances. The performance of the antenna is evaluated by monitoring RCS in the reader direction. The RCS of the designed tag is $-10.2\;dBm^2$ when the chip is shorted and is $-21\;dBm^2$ when the chip impedance is a complex conjugate of the antenna impedance.

• Journal of the Korea Society of Computer and Information
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• v.6 no.4
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• pp.12-20
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• 2001

The problem of software bottle-neck may be arised from unbalance of demands and supply of software. This is caused from the fact that the capability of programmer could not be improved in software development. Therefor, the new method of software development should aim at improving the productivity of software. This paper presents the expressions to be the standardized software Program modules by means of the software chip. The expressions are consist of name, input, output, and iteration of each software chip. And they simple express a combination and separation in sequence, parallel, iteration, composition, mixing, and variety form. Therefore they can easily software reuse as a result of analyzing the flow of data clearly.