• The Journal of Korean Institute of Electromagnetic Engineering and Science
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• v.14 no.7
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• pp.750-755
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• 2003

This paper proposes a new three-line balun. The equivalent circuit of the proposed three-line balun is presented, and impedance matrix［Z］of the equivalent circuit is derived from the relationship between the current and voltage at each port. The design equation for a given set of balun impedance at input and output ports is presented using［S］parameters, which is transferred fom impedance matrix,［Z］. To demonstrate the feasibility and validity of design equation, multi-layer ceramic(MLC) chip balun operated in the 2.4 GHz ISM band frequency is designed and fabricated by the use of the low temperature co-fired ceramic(LTCC) technology. By employing both the proposed new three-line balun equivalent circuit and multi-layer configuration provided by LTCC technology, the 2012 size MLC balun is realized. Measured results of the multi-layer LTCC three-line balun match well with the full-wave electromagnetic simulation results, and measured in band-phase and amplitude balances over a wide bandwidth are excellent. This proposed balun is very easily applicable to multi-layer structure using LTCC as shown in the paper, and also can be realized with microstrip lines on PCB. This distinctive performance is very favorable for wireless communication systems such as wireless LAN(Local Area Network) and Bluetooth applications.

• Journal of Life Science
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• v.14 no.5
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• pp.874-881
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• 2004

Angiogenesis has been implicated in progression of inflammation, arthritis, psoriasis, atherosclerosis as well as tumor growth and metastasis. Intensive studies have been carried out to develop a strategy for cancer treatment by blocking angiogenesis. During angiogenesis, endothelial proliferation and migration essentially occurs upon activation. In this study, we compared the expression profiles of human umbilical endothelial cells activated by incubating in vitro in the rich medium containing several growth factors, and non-activated ones. cDNA targets derived from total RNAs of HUVEC activated for 13 h in M199 medium containing endothelial cell growth supplement, 20% fetal bovine serum, and heparin, after reaching 70～80% confluency, or non-activated, were hybridized onto oligonucleotide microarrays containing 1,8864 genetic elements. Unsupervised hierarchical clustering analysis resulted in two subgroups on dendrogram exhibiting activated and non-activated HUVECs. We then extracted 122 outlier genes which were shown to be up-regulated or under-expressed by at least 2-folds in activated HUVECs. Among these, 32 annotated genes were up-regulated and 38 were down-regulated in activated HUVECs. Interestingly, genes involved in cell proliferation, motility, and inflammation/ immune response were up-regulated in activated HUVEC, whereas genes for cell adhesion or vessel morphogenesis/function were down-regulated. Unexpectedly, the expression of genes well-characterized as angiogenesis markers was not changed except Eph-B4, which was down-regulated about 4 folds. 52 unknown genes were also up- or down-regulated. Therefore, these results could provide an opportunity to targeting new vascular molecules for the development of anti-angiogenic molecules.

• Journal of the Institute of Electronics Engineers of Korea SP
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• v.49 no.4
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• pp.1-9
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• 2012

LCD(Liquid Crystal Display) commonly used as an output device has a drawback of slow response time compared with CRT display. This drawback causes motion blur especially when an abrupt intensity change occurs in an image sequence as time goes on. To overcome the problem of slow response time overdriving technique has been used in TCON of LCD. In this technique, the previous frame data has to be compressed and stored in an external memory. Considering both chip size of TCON and computational complexity, AM-BTC has been applied to the 8bit HD display driver. However, the conventional method is not suitable for 10 bit Full HD because 10 bit Full HD data is much larger than that of 8 bit HD data. Being applied to 10 bit Full HD display driver, the conventional method increase cost by enlarging the external memory size of TCON or deteriorates image quality. In this paper, we propose dual BTC image coding technique for Full HD display driver that is an adaptive coding scheme according to morphological information of each sample block. Through experiments, it is verified that the proposed Dual BTC method performs better than the conventional method not only quantitatively but also qualitatively.

• Journal of the Institute of Electronics Engineers of Korea SD
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• v.38 no.10
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• pp.712-720
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• 2001

Algorithms from the research of the layout migration were proposed in the paper. These are automatic recognition algorithm for the VLSI devices from it, graph based construction algorithm to maintain the constraints, dependencies, and design rule between the devices, and high speed compaction algorithm to reduce size of the VLSI area and reuse the design with compacted size for the new technology. Also, this paper describes that why proposed algorithms are essential for the era of the SoC (System on a Chip), design reuse, and IP DB, which are the big concerns in these days. In addition to introduce our algorithms, the benchmark showed that our performance is superior by 27 times faster than that of the commercial one, and has better efficiency by 3 times in disk usage.

• Journal of the Institute of Electronics Engineers of Korea SD
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• v.37 no.1
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• pp.75-82
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• 2000

In this paper, a new low power 16-bit ALU has been designed, fabricated and tested at the transistor level. The designed ALU performs 16 instructions and has a two-stage pipelined architecture. For the reduction of switched capacitance, the ELM adder of the proposed ALU is inactive while the logical operation is performed and P(propagation) block has a dual bus architecture. A new efficient P and G(generation) blocks are also proposed for the above ALU architecture. ELM adder, double-edge triggered register and the combination of logic style are used for low power consumption as well. As a result of simulations, the proposed architecture shows better power efficient than conventional architecture$^{[1,2]}$ as the number of logic operation to be performed is increased over that of arithmetic to logic operation to be performed is 7 to 3, compared to conventional architecture. The proposed ALU was fabricated with 0.6${\mu}m$ single-poly triple-metal CMOS process. As a result of chip test, the maximum operating frequency is 53MHz and power consumption is 33mW at 50MHz, 3.3V.

• Journal of the Institute of Electronics Engineers of Korea SD
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• v.47 no.3
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• pp.7-17
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• 2010

In this paper, an innovative low-power SRAM based on 4-transistor latch cell is described. The memory cells are composed of two cross-coupled inverters without access transistors. The sources of PMOS transistors are connected to bitlines while the sources of NMOS transistors are connected to wordlines. They are accessed by totally new read and write method which results in low operating power dissipation in the nature. Moreover, the design reduces the leakage current in the memory cells. The proposed SRAM has been demonstrated through 16-kbit test chip fabricated in a 0.18-${\mu}m$ CMOS process. It shows 17.5 ns access at 1.8-V supply while consuming dynamic power of $87.6\;{\mu}W/MHz$ (for read cycle) and $70.2\;{\mu}W/MHz$ (for write cycle). Compared with those of the conventional 6-transistor SRAM, it exhibits the power reduction of 30 % (read) and 42 % (write) respectively. Silicon measurement also confirms that the proposed SRAM achieves nearly 64 % reduction in the total standby power dissipation. This novel SRAM might be effective in realizing low-power embedded memory in future mobile applications.

• Journal of the Institute of Electronics Engineers of Korea SD
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• v.46 no.7
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• pp.68-73
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• 2009

This paper describes design and implementation of a spread spectrum clock generator (SSCG) for the DisplayPort. The proposed architecture generates the spread spectrum clock using a sigma-delta fractional-N PLL. The SSCG uses a digital End order MASH 1-1 sigma-delta modulator and a 9bit Up/Dn counter. By using MASH 1-1 sigma-delta modulator, complexity of circuit and chip area can be reduced. The advantage of sigma-delta modulator is the better control over modulation frequency and spread ratio. The SSCG generates dual clock rates which are 270MHz and 162MHz with 0.25% down-spreading and triangular waveform frequency modulation of 33kHz. The peak power reduction is 11.1dBm at 270MHz. The circuit has been designed and fabricated using in 0.18$\mu$m CMOS technology. The chip occupies 0.620mm$\times$0.780mm. The measurement results show that the fabricated chip satisfies the DispalyPort standard.

• The Journal of Korean Institute of Electromagnetic Engineering and Science
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• v.22 no.7
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• pp.683-693
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• 2011

In this paper, a design of high current and broad-band microwave bias-tee was presented for a stable bias of a high power amplifier. An input impedance of bias-tee should be shown to 50 ohm with the wideband in order to be stably-biased the amplifier. For this design of the bias-tee, a capacitor of bias-tee for a DC block was designed with a high wide-band admittance by a parallel sum of capacitors, and a inductor for a RF choke and a DC feeding was designed with a high wide-band impedance by a series sum of inductors. As this inductor and capacitor for the sum has each SRF, band-limitation of lumped element was driven from SRF. This limitation was overcome by control of a resonance's quality factor with adding a resistor. 1608 SMD chips for design's element was mounted on the this pattern for the designed bias-tee. The fabricated bias-tee presented 10 dB of return loss and wide-band about 50 ohm input impedance at 10 MHz~10 GHz.

• Journal of the Korea Academia-Industrial cooperation Society
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• v.18 no.12
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• pp.57-64
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• 2017

Today, due to the environmental regulations regarding air pollution in the EU, the use of EPS (Styrofoam) as the cushioning material in the packaging industry is decreasing. In effect, air cushioning based cushioning materials are rapidly expanding into the market and replacing EPS, due to their excellent buffering ability and environmental friendliness. This is a new selective filling type air filling material manufacturing technology that affords improvements in the amount of raw materials required, its processing and its aesthetic appearance compared to the conventional air filling cushioning materials. In this study, a multi-stage air cell filling valve molding technology is developed based on selective filling technology, which allows packages to be selectively filled in various forms by applying valve forming structure technology. This multi-stage air cell filling valve molding technology is a technique in which a plurality of injection ports are formed by laminating three layers of films, viz. a first injection film, a valve film, and a second injection film having valve ends. In the conventional technology, a separate external air injection path for injecting air into a plurality of connected air bags is needed. However, in the proposed system, an external air injection path is formed inside the air bag, Due to the lack of need for an injection furnace, the raw material and process are reduced and air is injected and then discharged, while the air bag is reduced in length to 63 ~ 66% of its normal value. The outer surface of the outer air injection path is integrated inside by maintaining the original length of the cross section, while the unnecessary folded air is injected into the interior of the air bag, This smart air filling type cushioning material manufacturing technology constitutes a big improvement over the existing technologies.

• Journal of Animal Science and Technology
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• v.47 no.5
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• pp.891-898
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• 2005

The trunk and limb of the Jindo, Korean native dog was measured in the present study. One hundred and ninety five Jindoes were randomly selected from the 1,985 dogs in the Jindo County in August 1998, which were screened by the judging committee of the County and registered by inserting electronic chips in the withers. They were about a year and half old, and were white and fawn dogs. A total of 18 parts of the trunk and limb were measured using calipers and tapes. The average height at the withers was 50.67 cm in dogs and 47.48 cm in bitches. The average body length was 52.99 cm in dogs and 50.33 cm in bitches. And the average height : body length ratio was 104.70 in dogs and 106.08 in bitches. No differences were observed between the Jindoes of the two coat colors in these measurements. The results of this study would be useful for compiling the official standard for the adult Jindo.