• Journal of the Institute of Convergence Signal Processing
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• v.2 no.3
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• pp.93-101
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• 2001

In this paper, we propose an image downscaler used in multimedia video applications, such as DTV, TV-PIP, PC-video, camcorder, videophone and so on. The proposed image downscaler provides a scaled image of high-quality and high-performance. This paper will explain the scaling theory using two-dimensional digital filters. It is the method that removes an aliasing noise and decreases the hardware complexity, compared with Pixel-drop and Upsamling. Also, this paper will prove it improves scaling precisians and decreases the loss of data, compared with the Scaler32, the Bt829 of Brooktree, and the SAA7114H of Philips. The proposed downscaler consists of the following four blocks: line memory, vertical scaler, horizontal scaler, and FIFO memory. In order to reduce the hardware complexity, the using digital filters are implemented by the multiplexer-adder type scheme and their all the coefficients can be simply implemented by using shifters and adders. It also decreases the loss of high frequency data because it provides the wider BW of 6MHz as adding the compensation filter. The proposed downscaler is modeled by using the Verilog-HDL and the model is verified by using the Cadence simulator. After the verification is done, the model is synthesized into gates by using the Synopsys. The synthesized downscaler is Placed and routed by the Mentor with the IDEC-C632 0.65${\mu}{\textrm}{m}$ library for further IC implementation. The IC master is fixed in size by 4,500${\mu}{\textrm}{m}$$\times$4,500${\mu}{\textrm}{m}$. The active layout size of the proposed downscaler is 2,528${\mu}{\textrm}{m}$$\times$3,237${\mu}{\textrm}{m}$.

• The Journal of Korean Institute of Electromagnetic Engineering and Science
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• v.22 no.12
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• pp.1069-1077
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• 2011

In this paper, a design and fabrication of a miniaturized 2.5 GHz 8 W power amplifier using selectively anodized aluminum oxide(SAAO) substrate are presented. The process of SAAO substrate is recently proposed and patented by Wavenics Inc. which uses aluminum as wafer. The selected active device is a commercially available GaN HEMT chip of TriQuint company, which is recently released. The optimum impedances for power amplifier design were extracted using the custom tuning jig composed of tunable passive components. The class-F power amplifier are designed based on EM co-simulation of impedance matching circuit. The matching circuit is realized in SAAO substrate. For integration and matching in the small package module, spiral inductors and single layer capacitors are used. The fabricated power amplifier with $4.4{\times}4.4\;mm^2$ shows the efficiency above 40 % and harmonic suppression above 30 dBc for the second(2nd) and the third(3rd) harmonic at the output power of 8 W.

• Korean Chemical Engineering Research
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• v.51 no.2
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• pp.214-220
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• 2013

Hydrophobic coating on a silicate-based yellow phosphor ($Sr_2SiO_4:Eu^{2+}$) was carried out by using hexamethyldisiloxane (HMDSO) precursor in an atmospheric pressure dielectric barrier discharge plasma reactor, eventually to improve the long-term stability and reliability of the phosphor. The phosphor powder samples were characterized by a scanning electron microscope (SEM), a transmission electron microscope (TEM), a fluorescence spectrophotometer and a contact angle analyzer. After the coating was prepared, the contact angle of the phosphor powder increased to $133.0^{\circ}$ for water and to $140.5^{\circ}$ for glycerol, indicating that a hydrophobic layer was formed on its surface. The phosphor coated with HMDSO exhibited photoluminescence enhancement up to 7.8%. The SEM and TEM images of the phosphor powder revealed that the plasma coating led to a morphological change from grain-like structure to smooth surface with 31~46 nm thick hydrophobic layer. The light emitting diode (3528 1 chip LED) fabricated with the coated phosphor showed a substantial enhancement in the reliability under a special test condition at $85^{\circ}C$ and 85% relative humidity for 1,000 h (85/85 testing). The plasma-mediated method proposed in this work may be applicable to the formation of 3-dimensional coating layer on irregular-shaped phosphor powder, thereby improving the reliability.

• Journal of the Institute of Electronics and Information Engineers
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• v.53 no.8
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• pp.113-118
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• 2016

In this paper, a read-in integrated circuit (RIIC) for IR scene projectors (IRSPs) adopting a sub-frame control technique is proposed, which minimizes the reduction of the apparent temperature of the IR images projected from IRSPs operating at a frame rate of 30 Hz. The proposed sub-frame control technique significantly reduces the amount of scene data loss on capacitors, which is caused by leakage currents flowing through MOSFET switches during holding periods, by dividing a unit frame into 8 sub-frames and refreshing the same scene data for each sub-frame. A current-drive RIIC was designed for the higher apparent temperature of IR radiated from the emitter, and it receives the scene data as a form of analog voltages from an external DAC. A prototype chip with a $64{\times}32$ RIIC array was fabricated using Magnachip/SKhynix $0.35{\mu}m$ 2-poly 4-metal CMOS process, and the measured maximum output data current is $230.3{\mu}A$. This amount of current ensures the projection of IR images whose maximum apparent temperature is $366.2^{\circ}C$ in the mid-wavelength IR (MWIR) when applied to a prototype emitter having a resistance of $15k{\Omega}$.

• The Journal of Korean Institute of Electromagnetic Engineering and Science
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• v.16 no.7 s.98
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• pp.753-759
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• 2005

In this paper, we have developed a new type of single balanced mixer with the RF MEMS $180^{\circ}$ hybrid coupler using surface micromachining technology. The $180^{\circ}$ hybrid coupler in this mixer is composed of the dielectric-supported air gapped microstriplines(DAMLs) which have signal line with $10{\mu}m$ height to reduce substrate dielectric loss and dielectric posts with size of $20{\mu}m{\times}20{\mu}m$ to elevate the signal line on air with stability At LO power of 7.2 dBm, the conversion loss was 15.5 dB f3r RF frequency or 57 GHz and RF power of -15 dBm. Also, we obtained the good RF to LO isolation of -40 dB at LO frequency of 58 GHz and LO power of 7.2 dBm. The main advantage of this type of mixer is that we are able to reduce the size of the chips due to integrating the MEMS passive components.

• International Journal of Highway Engineering
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• v.13 no.4
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• pp.231-238
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• 2011

Variable message signs(VMS) in use are being displaying with the LED device as the luminous source, and it is a recent trend to be changed from the Lamp type to the Surface-Mount Devices(SMD) type. The LED device leads to get VMS display brightly and clearly, leading to have visibility and legibility better than the existing VMS. However, the lights which display off the road, the unnecessary energy, might have negative effect on ecosystem. This study developed the way of getting the lights be displayed only to drivers without the unnecessary energy and estimated the energy efficiency of the development by the optical testing. As a result, this study showed that the energy consumption of the developed display device appeared to decrease by about 36.1% compared to the existing device. Also the upward and downward angle of the lights changed from an angle of $24^{\circ}C$ to $0^{\circ}C$and from an angle of $-24^{\circ}C$ to $-11^{\circ}C$, respectively. Therefore, it anticipates that the developed device would benefit highway safety due to an improvement in visibility and legibility compared to the existing VMS and the energy consumption would be less lower than the existing VMS.

• Korean Chemical Engineering Research
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• v.44 no.5
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• pp.513-519
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• 2006

We developed two kinds of the microchip for application to electrophoresis based on both glass and quartz employing the MEMS fabrications. The poly-Si layer deposited onto the bonding interface apart from channel regions can play a role as the optical slit cutting off the stray light in order to concentrate the UV ray, from which it is possible to improve the signal-to-noise (S/N) ratio of the detection on a chip. In the glass chip, the deposited poly-Si layer had an important function of the etch mask and provided the bonding surface properly enabling the anodic bonding. The glass wafer including more impurities than quartz one results in the higher surface roughness of the channel wall, which affects subsequently on the microflow behavior of the sample solutions. In order to solve this problem, we prepared here the mixed etchant consisting HF and $NH_4F$ solutions, by which the surface roughness was reduced. Both the shape and the dimension of each channel were observed, and the electroosmotic flow velocities were measured as 0.5 mm/s for quartz and 0.36 mm/s for glass channel by implementing the microchip electrophoresis. Applying the optical slit with poly-Si layer provides that the S/N ratio of the peak is increased as ca. 2 times for quartz chip and ca. 3 times for glass chip. The maximum UV absorbance is also enhanced with ca. 1.6 and 1.7 times, respectively.

• The Journal of the Institute of Internet, Broadcasting and Communication
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• v.14 no.6
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• pp.149-157
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• 2014

This paper is based on the fabrication of wireless control system for the building shading device. RF Module was controlled by UHF wireless CC1020 chip which has low electrical power and low electrical voltage. Also 447.8625~447.9875 frequency, 4800Baud data rate and 12.5 kHz channel spacing was controlled by the use of SPDT switch and with Microcontroller program. Furthermore, the helical antenna was used. The starting production of 447.8625~447.9875 kHz wireless electrical power was used. As the result, it did not exceed 10dBm which is the standard of low power wireless system. Shading efficiency was measured at 25%, 50%, 75% direction with controlling the interior temperature and the intensity of illumination at the rate of 1 hour. As the result, the intensity of illumination was lowered to 82~87% at 25% direction with $0.6{\sim}1.4^{\circ}C$ lowered temperature. At 50% direction, the intensity of illumination was lowered to 60~68% with $2.3{\sim}4.1^{\circ}C$ lowered temperature. And at 75% direction, the intensity of illumination was lowered to 41~47% with $3.4{\sim}5.1^{\circ}C$ lowered temperature.

• Journal of the Microelectronics and Packaging Society
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• v.21 no.1
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• pp.31-39
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• 2014

For mobile application, semiconductor packages are increasingly moving toward high density, miniaturization, lighter and multi-functions. Typical wafer level packages (WLP) is fan-in design, it can not meet high I/O requirement. The fan-out wafer level packages (FOWLPs) with reconfiguration technology have recently emerged as a new WLP technology. In FOWLP, warpage is one of the most critical issues since the thickness of FOWLP is thinner than traditional IC package and warpage of WLP is much larger than the die level package. Warpage affects the throughput and yield of the next manufacturing process as well as wafer handling and fabrication processability. In this study, we investigated the characteristics of warpage and main parameters which affect the warpage deformation of FOWLP using the finite element numerical simulation. In order to minimize the warpage, the characteristics of warpage for various epoxy mold compounds (EMCs) and carrier materials are investigated, and DOE optimization is also performed. In particular, warpage after EMC molding and after carrier detachment process were analyzed respectively. The simulation results indicate that the most influential factor on warpage is CTE of EMC after molding process. EMC material of low CTE and high Tg (glass transition temperature) will reduce the warpage. For carrier material, Alloy42 shows the lowest warpage. Therefore, considering the cost, oxidation and thermal conductivity, Alloy42 or SUS304 is recommend for a carrier material.

• Journal of the Korean Institute of Telematics and Electronics C
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• v.36C no.12
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• pp.11-19
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• 1999

Fractal image compression algorithm has been studied mostly not in the view of hardware but software. However, a general processor by software can't decode fractal compressed images in real-time. Therefore, it is necessary that we develop a fast dedicated hardware. However, design examples of dedicated hardware are very rare. In this paper, we designed a quadtree fractal-based compressed image decoder which can decode $256{\times}256$ gray-scale images in real-time and used two power-down methods. The first is a hardware-optimized simple post-processing, whose role is to remove block effect appeared after reconstruction, and which is easier to be implemented in hardware than non-2' exponents weighted average method used in conventional software implementation, lessens costs, and accelerates post-processing speed by about 69%. Therefore, we can expect that the method dissipates low power and low energy. The second is to design a power dissipation in the multiplier can be reduced by about 28% with respect to a general array multiplier which is known efficient for low power design in the size of 8 bits or smaller. Using the above two power-down methods, we designed decoder's core block in 3.3V, 1 poly 3 metal, $0.6{\mu}m$ CMOS technology.