• The Journal of Korean Institute of Electromagnetic Engineering and Science
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• v.18 no.4 s.119
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• pp.364-371
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• 2007

In this paper, the design and implementation of high-power PIN diode switch modules and high-speed switch driver circuits are presented for Wibro base stations. To prevent isolation degradation due to parasitic inductances of conventional packaged PIN diodes and to improve power handling capabilities of the switch modules, bare diode chips are used and carefully placed in a PCB layout, which makes bonding wire inductances to be absorbed in the impedance of a transmission line. The switch module is designed and implemented to have a maximum performance while using a minimum number of the diodes. It shows an insertion loss of ${\sim}0.84\;dB$ and isolation of 80 dB or more at 2.35 GHz. The switch driver circuit is also fabricated and measured to have a switching speed of ${\sim}200\;nsec$. The power handling capability test demonstrates that the module operates normally even under a digitally modulated 70 W RF signal stress.

• Journal of Satellite, Information and Communications
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• v.7 no.3
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• pp.26-29
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• 2012

In this paper, we propose a Single Carrier Frequency Division Multiple Access(SC-FDMA) scheme with greatly enhanced tolerance of timing offset among the users. The type of the proposed scheme is similar to code spread Multiple Carrier Direct Spread Code Division Multiple Access(MC DS CDMA). The proposed scheme performs partial Discrete Fourier Transform(DFT) in order to solve high Peak to Average Power Ratio(PAPR) of the MC DS CDMA before Inverse Fast Fourier Transform(IFFT). Exploiting the property Properly Scrambled Walsh-Hadamard(PSW) code has zero correlation despite ${\pm}1$ chip timing offset, the proposed scheme achieves Multiple Access Interference free performance with the timing offset up to ${\pm}1$ OFDM symbol duration with low PAPR. In contrast, the other existing schemes in comparison undergo severe performance degradation even with small timing offset in multipath fading channel.

• Journal of the Korean Institute of Illuminating and Electrical Installation Engineers
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• v.24 no.6
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• pp.8-17
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• 2010

This paper proposes a novel LCD CCFL-backlight electronic ballast using the phase-shift full-bridge inverter. The proposed electronic ballast reduces the ignition voltage and eliminates current spikes using the new digital dimming control applied with soft-starting. Thus the electronic ballast improves ignition behavior of the CCFL and hence increases the CCFL's life span. For this, this paper analyzes the full-bridge inverter topology of the proposed electronic ballast and explains the new digital dimming control algorithm applied to the ballast, briefly. And this paper shows a design example of the prototype circuit and explains an implementation method of the digital dimming control which is implemented on a single-chip microcontroller with software. This was implemented as actual prototype electronic ballast, and its experimental results showed that the proposed electronic ballast operates correctly. The ignition voltage of the prototype in the digital dimming operation was reduced about 30[%] compared with the conventional electronic ballast and there were not any current spikes.

• Journal of the Korea Institute of Information and Communication Engineering
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• v.20 no.12
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• pp.2326-2332
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• 2016

In this paper, the proposed small size PLL works stable with the discrete loop filter which is controlled by voltage controlled oscillator's output signal. A switch controlled loop filter is introduced into the proposed PLL instead of a conventional $2^{nd}$-order loop filter. Those three switches are controlled by the very high frequency output signal of voltage controlled oscillator. The switches are also controlled by UP/DN signals and 'on/off' depending the presence of UP/DN signals. A negative feedback functioned capacitor with a switch does make it possible to integrate the PLL into a single chip. The proposed PLL works stably even though a total of small 180pF capacitor used in the discrete loop filter. The proposed PLL has been designed with a 1.8V supply voltage, 0.18um multi - metal and multi - poly layer CMOS process and proved by Hspice simulation.

• Korean Journal of Optics and Photonics
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• v.14 no.5
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• pp.504-508
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• 2003

We present a new point-diffraction interferometer, which has been devised for the three-dimensional profile measurement of light scattering rough surfaces. The interferometer system has multiple sources of two-point-diffraction and a CCD camera composed of an array of two-dimensional photodetectors. Each diffraction source is an independent two-point-diffraction interferometer made of a pair of single-mode optical fibers, which are housed in a ceramic ferrule to emit two spherical wave fronts by means of diffraction at their free ends. The two spherical wave fronts then interfere with each other and subsequently generate a unique fringe pattern on the test surface. A He-Ne source provides coherent light to the two fibers through a 2${\times}$l optical coupler, and one of the fibers is elongated by use of a piezoelectric tube to produce phase shifting. The xyz coordinates of the target surface are determined by fitting the measured phase data into a global model of multilateration. Measurement has been performed for the warpage inspection of chip scale packages (CSPs) that are tape-mounted on ball grid arrays (BGAs) and backside profile of a silicon wafer in the middle of integrated-circuit fabrication process. When a diagonal profile is measured across the wafer, the maximum discrepancy turns out to be 5.6 ${\mu}{\textrm}{m}$ with a standard deviation of 1.5 ${\mu}{\textrm}{m}$.

• The Journal of Korean Institute of Electromagnetic Engineering and Science
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• v.19 no.9
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• pp.978-984
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• 2008

In this paper, we propose a RFID metal tag antenna with a minimum by size of a metal surface to attach. This proposed tag antenna is a patch antenna which is able to stick on metal surface and designed for very slim structure ($119{\times}30{\times}1.6$ mm) antenna that is matched to a chip impedance. This has a loop coupling feeding and consists of a inner radiator and a outer radiator. The outer radiator activates the current to concentrate on the inner radiator regardless of metal size to attach. Also the tag antenna is designed by CST microwave tool and the performance is measured in the anechoic chamber. The optimum antenna has 3.77 % of the matching bandwidth($S_{11}<-10$ dB). The readable range of the tag antenna is about 2.9 m on metal(max. size $700{\times}700$ mm) and 5.5 m in free space according to the measurement results.

• Journal of the Korea Institute of Information and Communication Engineering
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• v.13 no.2
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• pp.293-298
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• 2009

In this contribution, a 193-bit elliptic curve cryptography coprocessor was implemented on an FPGA board. Optimized algorithms and numerical expressions which had been verified through C program simulation, should be analyzed again with HDL (hardware description language) such as Verilog, so that the verified ones could be modified to be applied directly to hardware implementation. The reason is that the characteristics of C programming language design is intrinsically different from the hardware design structure. The hardware IP which was double-checked in view of hardware structure together with algoritunic verification, was implemented on the Altera CycloneII FPGA device equipped with ARM9 microprocessor core, to a real chip prototype, using Altera embedded system development tool kit. The implemented finite field calculation IPs can be used as library modules as Elliptic Curve Cryptography finite field operations which has more than 193 bit key length.

• Journal of the Institute of Electronics Engineers of Korea TC
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• v.48 no.1
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• pp.102-107
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• 2011

The current blood control system is using barcode and scanning one by one to manage blood bags. To have better management and accuracy, an RFID BIS (blood information system) is implemented with an UHF RFID tag antenna using a reflecter for a blood bag has been used.. The UHF RFID tag for blood bag, attached on the high permittivity blood, is designed and fabricated. The tag antenna is optimized and fabricated with the simulation tests such as the existence and nonexistence of the reflector, various distance between the reflector and the dipole tag, the different widths of the reflector and the existence and nonexistence of the T-matching structure. The characteristics and the reading range patterns of the tag antennas are measured. The BIS is implemented with the new tag design.

• Journal of the Institute of Electronics and Information Engineers
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• v.51 no.6
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• pp.261-268
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• 2014

This paper presents a electrocardiogram(ECG), electromyogram(EMG), and Photoplethysmography(PPG) signal wireless monitoring system based on Bluetooth Low Energy (BLE). ECG and EMG sensor interface analog front-end circuits are designed by using off-the-shelf parts. Texas Instruments(TI)'s CC2540DK is used for BLE-based communication. Two CC2540DK modules are used as Peripheral and Central nodes. In peripheral device, vital signals are acquired by the analog front-ends and fed to ADC for analog-to-digital conversion. The peripheral transmitts the data through the air to the central device. The central device receive the data and sends them to PC using UART. GUI is designed using Labview for displaying the acquired vital signals. The developed system can be used for future ubiquitous wireless healthcare system based on bluetooth 4.0.

• The Journal of Korean Institute of Electromagnetic Engineering and Science
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• v.14 no.10
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• pp.1036-1043
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• 2003

In this paper, novel lumped equivalent circuits for a conventional parallel directional coupler are proposed. This novel equivalent circuits only have self inductance and self capacitance, so we can design exact lumped equivalent circuit. The equivalent circuit and design formula for the presented lumped element coupler is derived based on the even- and odd-mode properties of a parallel-coupled line. By using the derived design formula, we have designed the 3 dB and 10 dB lumped element directional couplers at the center frequency of 100 MHz and 2 GHz, respectively a chip type directional coupler has been designed with multilayer configurations by employing commercial EM simulator. Designed chip-type directional couplers have a 3 dB-coupling value at the center frequency of 2 GHz and fabricated lumped directional coupler on fr4 organic substrate has a 3 dB, 10 dB-coupling values at the center frequency of 100 MHz. Excellent agreements between simulation results and measurement results on the designed directional couplers show the validity of this paper. Furthermore, in order to adapt to multi-layer process such as Low Temperature Cofired Ceramic (LTCC), chip-type lumped element couplers have been designed by using this method.