• The Journal of Korean Institute of Communications and Information Sciences
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• v.15 no.6
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• pp.455-466
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• 1990

Enalish character recognition with the neural networl algorithm has been performed. Character recognition technition techniques which are processed by software, have the limit of the recognition speed. To overcome this limit, we realize this system to hardware by using the neural network algorithm. We have designed preprocessing chip using the neural nework model, that is single layer perceptorn, in the noise elimination, smoothing, thinning and feature point extraction. These chips are implemented as a CMOS double metal 2um design rule.

• Proceedings of the KIEE Conference
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• 1999.07g
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• pp.2812-2814
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• 1999

그레이 영상 입출력이 가능하고, 다양한 영상 크기에 적용 가능한 아날로그 셀룰라 신경회로망을 설계하였다. 아날로그 셀룰라 신경회로망은 실시간 병렬처리가 가능하므로, 영상처리 패턴인식과 같은 분야에 유용하게 사용될 수 있다. 기존의 하드웨어로 구현된 셀를라 신경회로망은 이진 영상를 출력하고, 단일 칩에 구현할 수 있는 셀의 수에 제한이 있기 때문에 범용의 영상처리에 응용하기에 적합지 않다. 본 연구에서 설계된 셀룰라 신경회로망은 영상 입력 크기의 분해능을 향상시켜 그레이 영상 처리가 가능한 칩을 설계하였다. 설계된 셀룰라 신경회로망를 이용한 그레이 영상의 에지추출 시뮬레이션 결과, 선명한 에지 영상을 얻을 수 있었다

• Proceedings of the Korean Information Science Society Conference
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• 2001.10c
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• pp.43-45
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• 2001

본 논문에서는 한국정보보호 진흥원예서 표준으로 개발한 128비트 블록암호 알고리즘의 표준인 SEED를 하드웨어 칩으로 설계 연구하였다. 설계 연구 방법은 기존 암호 연산부의 속도 개선의 한 방법으로 암호 블록의 16 라운드 각각을 하나의 프로세서로 보고, 이를 파이프라인 방식으로 설계하여 암호 연산의 속도를 증진시키는 방법으로 설계하였다. Cadence의 NCVHDL로 Functional Simulation하고, Synopsys의 Compiler II로 Optimize된 Schematic을 검증하였다.

• Journal of the Institute of Electronics Engineers of Korea SD
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• v.44 no.3 s.357
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• pp.26-34
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• 2007

This Paper describes a chip design technique for body composition analyzer based on the BIA (Bioelectrical Impedance Analysis) method. All the functions of signal forcing circuits to the body, signal detecting circuits from the body, Micom, SRAM and EEPROMS are integrated in one chip. Especially, multi-frequency detecting method can be applied with selective band pass filter (BPF), which is designed in weak inversion region for low power consumption. In addition new full wave rectifier (FWR) is also proposed with differential difference amplifier (DDA) for high performance (small die area low power consumption, rail-to-rail output swing). The prototype chip is implemented with 0.35um CMOS technology and shows the power dissipation of 6 mW at the supply voltage of 3.3V. The die area of prototype chip is $5mm\times5mm$.

• The Journal of the Korea institute of electronic communication sciences
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• v.8 no.10
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• pp.1427-1434
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• 2013

In this paper, triple band mobile chip antenna for DCS(1.71~1.88GHz) / PCS(1.75~1.87GHz) / UPCS(1.85~1.99GHz) on PCB Layout is designed. To analyze the characteristics of the designed antenna, we designed and measured Single, Dual, Triple Band antenna. The designed antenna was fabricated and measured using vector network analyzer in LTK(Laird Technologies Korea). Triple and wide band characteristic could be realized the measured bandwidth(V.S.W.R<2.0) of designed antenna operated in the band of 1.71GHz~1.99GHz. This antenna has a small size of about $19mm{\times}4mm{\times}1.6mm$, narrow bandwidth which is a defect of chip antenna is improved. And its experimental results were a good agreement with simulation performance.

• Proceedings of the Korea Society for Simulation Conference
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• 1997.04a
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• pp.31-35
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• 1997

본 논문에서는 암호화 알고리즘의 하나인 GOST (Government Standard)를 칩으로 구현했을 경우에 차지하는 면적과 속도에 대해 DES와 비교 분석하고, GDES의 구조를 이 용하여 GOST 알고리즘을 빠르게 처리할 수 있도록 설계하였다. 합성한 것을 최종적으로 MAX+plus II를 이용하여 시뮬레이션을 통해 검증하였다.

• Journal of Sensor Science and Technology
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• v.11 no.5
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• pp.255-262
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• 2002

Human retina is able to detect the edge of an object effectively. We designed a CMOS vision chip by modeling cells of the retina as hardwares involved in edge detection. There are several fluctuation factors which affect characteristics of MOSFETs during CMOS fabrication process and this effect appears as output offset of the vision chip which is composed of pixel arrays and readout circuits. The vision chip detecting edge information from input image is used for input stage of other systems. Therefore, the output offset of a vision chip determine the efficiency of the entire performance of a system. In order to eliminate the offset at the output stage, we designed a vision chip by using CDS(Correlated Double Sampling) technique. Using standard CMOS process, it is possible to integrate with other circuits. Having reliable output characteristics, this chip can be used at the input stage for many applications, like targe tracking system, fingerprint recognition system, human-friendly robot system and etc.

• The Journal of Korean Institute of Communications and Information Sciences
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• v.23 no.4
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• pp.988-996
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• 1998

BN ceramics with 0.07wt% $V_{2}O_{5}$ and 0.03wt% CuO(BNC3V7) sintered at $900^{\circ}C$ where it is possible for these to be co-fired with Ag electrode. Dielectricconstant of 44.3, TCF of 22 ppm$/^{\circ}C$ and $Qxf_{o}$ value of 22,000 GHz can be obtained from BNC3V7, multilayer type band pass filters using tapped method and conventional method were designed for PCS (Personal Communication System) applications. Tapped method by adopting input/output-tapping scheme the chip filter stucture becomes simpler and needs fewer layers than that using the conventional input/output-coupling scheme. A multilayer type band pass filter fabricated by screen-printing with silver electrode after tape casting. The simulated characteristics of the fabricated filters sintered at $900^{\circ}C$ were compared with the designed ones. Even though the centered frequencies of tapped and conventional band pass chaip filters were measured to shift about 90MHz downward, the band pass characteristics of both filters were similar that of designed ones. The spuriousresonance characteristic of tapped pass chip filter was better than that of conventional chip filer.

• Proceedings of the Korean Institute of Information and Commucation Sciences Conference
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• 2001.05a
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• pp.345-348
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• 2001

The paper describes the physical design flow & verification of Digital Video Broadcasting(DVB) compliant satellite receiver chip. It includes problems and issues of earth design flow, verification process for physical layout.

• Proceedings of the Korean Institute of Information and Commucation Sciences Conference
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• 2003.10a
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• pp.990-994
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• 2003

This paper describes the VoIP(Voice over Internet Protocol) SoC(System on Chip) Design and the test board development for the function verification to support voice communication services using Internet. To implement the simple system of configuration, we designed the VoIP SoC which have ARM922T of 32bit microprocessor, IP network interface, voice signal interface, various user interface function. Also we developed test program and communication protocol to verify the function of this chip. We used several tools of design and simulation, developed and tested a test board with Excalibur which includes ARM922T microprocessor and FPGA.