• The Journal of Korean Institute of Communications and Information Sciences
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• v.23 no.8
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• pp.1941-1951
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• 1998

In this paper, hardware circuit that performs functions of IEEE 802.11 wireless LAN frequency hopping PLCP protocol is designed using 0.8 um CMOS cmn8a technology of the COMPASS. Transmission rate of the designed hardware is 1Mbps. The designed circuit have about 6300 gates and $2.5{\times}2.5mm^2$ area. In order to verify the circuit, two PLCP circuits are interconnected and frames are transmitted from one PLCP circuit to the other PLCP circuit. As a results of the simulation, we conclude that the designed PLCP circuit works well as the IEEE 802.11 standard specification.

• Journal of the Korea Academia-Industrial cooperation Society
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• v.10 no.7
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• pp.1480-1483
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• 2009

In this paper, the hardware(HW) and software(SW) co-design methodology of H.264/AVC decoder using ARM-Excalibur is proposed. The SoC consists of embedded processor, memory, peripheral device and logic circuits. Recently, the co-design method which designs simultaneously HW and SW part is a new paradigm in SoC design. Because the optimization for partitioning the SoC system is very difficult, the verification must be performed earlier in design flow. We designed the H.264 and AVC Decoder using co-design method. It is shown that, for the proposed co-design method, the performance improvements can be obtained.

• Broadcasting and Media Magazine
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• v.12 no.4
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• pp.21-27
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• 2007

• The Magazine of the IEIE
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• v.38 no.10
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• pp.42-48
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• 2011

• The Magazine of the IEIE
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• v.37 no.10
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• pp.48-62
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• 2010

• Proceedings of the International Microelectronics And Packaging Society Conference
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• 2004.11a
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• pp.12-13
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• 2004

• IT SoC Magazine
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• s.11
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• pp.34-39
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• 2006

• The Magazine of the IEIE
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• v.43 no.7
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• pp.18-24
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• 2016

• Transactions of the Korean Society of Mechanical Engineers B
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• v.36 no.9
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• pp.901-905
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• 2012

We present an electroporation and viability monitoring chip for lung cancer cells in a single channel with multiple electric field zones. Previous electroporation chips utilized multiple microchannels or electrodes to form multiple electric fields, thus resulting in complex structures. However, the present chip can generate multiple electric fields in a single stepwise microchannel between a pair of electrodes, thus achieving the analysis of both cell electroporation and viability with a simple structure. We demonstrate that the electric field of 0.4 kV/cm results in a maximum percentage of $51.4{\pm}3.0%$ and $26.6{\pm}0.7%$ of viable and electroporated human lung cancer cells, H23 and A549, respectively. The present chip has potential for use in integrated cell chips for transfection studies.

• The Journal of Korean Institute of Electromagnetic Engineering and Science
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• v.24 no.10
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• pp.964-970
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• 2013

This paper presents a bandpass wireless 3-D chip to chip interface technique. The proposed technique uses direct amplitude modulation of the free running oscillator which especially utilizes the coupling capacitance between two stacked chips as a part of the resonator. Therefore, the oscillator is three dimensionally configured and a simple envelope detector can be used as a receiver without any additional matching circuitry. The proposed link was designed and fabricated using 110 nm CMOS technology and experimental results successfully showed the data transmission at a data rate of 2 Gb/s for the stacked chips with a thickness of 50 ${\mu}m$ consuming 4.32 mW. The sizes of the Tx and Rx chips are 0.045 $mm^2$ and 0.029 $mm^2$, respectively.