• Journal of Software Assessment and Valuation
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• v.15 no.1
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• pp.55-62
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• 2019

The needs for small size and low power consumption of information devices is being implemented with SOC technology that implements the program on a single chip in Internet of Thing. Copyright disputes due to piracy are increasing in semiconductor chips as well, arising from disputes in the chip implementation of the design house and chip implementation by the illegal use of the source code. However, since the final chip implementation is made in the design house, it is difficult to protect the copyright. In this paper, we deal with the analysis method for extracting similarity and the criteria for setting similarity judgment in the dispute of source code written in HDL language. Especially, the chip which is manufactured based on the same specification will be divided into the same configuration and the code type.

• Journal of the Korean Institute of Telematics and Electronics C
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• v.36C no.12
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• pp.20-26
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• 1999

A CMOS 6-bit 100MSPS ADC for DBS receiver is designed. The proposed ADC is composed of folding block, latch block, and digital block. The cascode interpolating block and kickback reduced latch are proposed with a high speed architecture. To verify the performance of ADC, simulations are carried out by HSPICE. The ADC achieves a clock frequency of 100MHz with a power dissipation of 40mW for 3 V supply voltage. The active chip area is $1500{\mu}m{\times}1000{\mu}m$with $0.65{\mu}m$ 2-poly 2-metal CMOS process. Further, INL and DNL are within ${\pm}0.6LSB$, ${\pm}0.5LSB$, respectively. SNDR is about 33dB at 10MHz input frequency.

• The Journal of Korean Institute of Electromagnetic Engineering and Science
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• v.20 no.3
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• pp.264-272
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• 2009

In this paper, a Ka-band 10 W power amplifier module is designed and fabricated using MIC(Microwave Integrated Circuit) module technology which combines multiple power MMIC(Monolithic Microwave Integrated Circuit) chips on a thin film substrate. Modified Wilkinson power dividers/combiners are used for millimeter wave modules and CBFGC-PW-Microstrip transitions are utilized for reducing connection loss and suppressing resonance in the high-gain and high-power modules. The power amplifier module consists of seven MMIC chips and operates in a pulsed mode. for the pulsed mode operation, a gate pulse control circuit supplying the control voltage pulses to MMIC chips is designed and applied. The fabricated power amplifier module shows a power gain of about 58 dB and a saturated output power of 39.6 dBm at a center frequency of the interested frequency band.

• The Journal of Korean Institute of Electromagnetic Engineering and Science
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• v.30 no.6
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• pp.518-521
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• 2019

In this paper, an active antenna module operating in the 60 GHz band is designed and fabricated by combining a commercial transmitter chip and patch array antenna. The designed module is composed of an antenna PCB and a PCB with a transmitter chip. The frequency-control and bias-control signals are applied to the transmitter chip, using an Arduino kit. A baseband I/Q signal is also applied to the chip. A ring hybrid balun converts the output of the transmitter module to a single output, which is the output of the transmitter chip that outputs a differential output. The output is delivered to the $2{\times}4$ microstrip patch array antenna PCB as a micro-computer connector. The radiation pattern of the millimeter-wave signal of the final output is compared with the simulation results. The measured radiation patterns of the fabricated active antenna module confirm that the positions of the 3 dB beam width and null point agree well with the simulation results.

• Journal of Platform Technology
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• v.8 no.1
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• pp.24-32
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• 2020

This paper designed and manufactured a chip mounter based on 3D printer technology that can be used for educational research or sample production to disseminate chip mounter, a core technology of SMT line. A stepper motor with open loop control is used for low cost drive design. The shortcomings of the motor's vibration and disassembly caused by the use of the step motor were compensated by the Micro-Step control method. In the chip mounter experiment, the gerber file was generated on the small chip mounter, printed at the actual size, and the solder cream was printed on the HASL-treated PCB in the same manner as the sample board fabrication. As a result of the experiment, unlike the 2012 micro components, parts such as SOIC and TQFP that require correction are twice as long as the component mounting time, but it can be confirmed that they are mounted relatively accurately. In addition, as a result of repeatedly measuring the error of the initial position 10 times, it was confirmed that a relatively small error of about 0.110mm occurs.

• Journal of the Institute of Electronics and Information Engineers
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• v.51 no.11
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• pp.83-93
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• 2014

It is a widespread concern that electrical interconnection based network-on-chip (NoC) will ultimately face the limitation in communication bandwidth, transmission latency and power consumption in the near future. With the development of silicon photonics technology, a hybrid optical network-on-chip (HONoC) which embraces both electrical- and optical interconnect, is emerging as a promising solution to overcome these problems. Today's leading edge systems-on-chips (SoCs) comprise heterogeneous many-cores for higher energy efficiency, therefore, extended study beyond regular topology based NoC is required. This paper proposes an energy and latency optimization topology design technique for HONoC taking into account the traffic characteristics of target applications. The proposed technique is implemented with genetic algorithm and simulation results show the reduction by 13.84% in power loss and 28.14% in average latency, respectively.

• The Journal of Korean Institute of Communications and Information Sciences
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• v.25 no.9A
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• pp.1332-1339
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• 2000

This paper presents the architecture and design of a high speed asymmetric data transmission baseband MODEM ASIC chip for CATV networks. The implemented MODEM chip supports the physical layer of the DOCSIS(Data Over Cable Service Interface Specification) standard in MCNS(Multimedia Cable Network System) The chip consists of a QPSK/16-QAM transmitter and a 64/256-QAM receiver which contain a symbol timing recovery circuit, a carrier recovery circuit, a blind equalizer using MMA and LMS algorithms. The chip can support data rates of 64Mbps at 256 QAM and 48Mbps at 64-QAM and can provide symbol rates up to 8MBaud. This symbol rate is faster than existing QAM receivers. We have performed logic synthesis using the $0.35\mu\textrm{m}$ standard cell library. The total number of gates is about 290,000 and the implemented chip is being fabricated and will be delivered soon.

• The Journal of Korean Institute of Electromagnetic Engineering and Science
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• v.29 no.5
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• pp.336-343
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• 2018

We herein present the design and fabrication of a Rx core chip operating in the X-band (10.5~13 GHz) using Win's commercial $0.25-{\mu}m$ GaAs pHEMT process technology. The X-band core chip comprises a low-noise amplifier, a four-bit phase shifter, and a serial-to-parallel data converter. The size is $1.75mm{\times}1.75mm$, which is the state-of-the-art size. The gain and noise figure are more than 10 dB but less than 2 dB, and both the input and output return losses are less than 10 dB. The RMS phase error is less than $5^{\circ}$, and the P1dB is 2 dBm at 12.5 GHz, the performance of which is equivalent to other GaAs core chips. The fabricated core chip was packaged in a QFN package type with a size of $3mm{\times}3mm$ for the convenience of assembly. We confirmed that the performance of the packaged core chip was almost the same as that of the chip itself.

• The Journal of the Institute of Internet, Broadcasting and Communication
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• v.19 no.6
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• pp.175-181
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• 2019

For the purpose of Application to the small radar sensor, the MMIC Chip, which is the core component of the W-band, was designed in Korea according to the characteristics of the transceiver and manufactured by 0.1㎛ GaAs pHEMT process, and compared with the MMIC chip purchased overseas. The noise figure of low noise amplifier, insertion loss of the switch and image rejection performance of the down-converted mixer MMIC chip showed better characteristics than those of commercial chips. The MMIC chip developed in domestic was applied to the transmitter and receiver through W-band waveguide low loss transition structure design and impedance matching to verify the performance after the fabrication is 9.17 dB, which is close to the analysis result. As a result, it is judged that the transceiver can be applied to the small radar sensor better than the MMIC chip purchased overseas.

• Journal of the Institute of Electronics and Information Engineers
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• v.52 no.3
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• pp.96-101
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• 2015

This paper describes a design and implementation of the NFC bridge chip which performs interface between kinds of devices and mobile phones including NFC controller through NFC communication. The NFC bridge chip consists of the digital part and the analog part which are based on NFC Forum standard. Therefore the chip treats RF signals and then transforms the signal to digital data, so it can interface kinds of devices with the digital data. Especially the chip is able to detect RF signals and then wake up the host processor of a device. The wakeup function dramatically decreases the power consumption of the device. The carrier frequency is 13.56MHz, and the data rate is up to 424kbps. The chip has been fabricated with SMIC 180nm mixed-mode technology. Additionally an NFC bridge chip application to the blood glucose measurement system is described for an application example.