• Journal of the Institute of Electronics Engineers of Korea TC
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• v.48 no.1
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• pp.77-83
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• 2011

In this thesis, 50W Doherty amplifier was designed and implemented for Beyond 3G's repeater and base-station. Auxiliary amplifier of doherty amplifier was implemented by Gate bias control circuit. Though gate bias control circuit solved auxiliary's bias problem, output characteristics of doherty amplifier was limited. To enhance the output characteristic relativize Drain control circuit And To improve power efficiency make 3-way Doherty power amplifier. therefore, 3-way GDCD (Gate and Drain bias Control Doherty) power amplifier is embodied to drain bias circuit for General Doherty power amplifier. The 3-way GDCD power amplifier composed of matching circuit with chip capacitor and micro strip line using FR4 dielectric substance of specific inductive capacity(${\varepsilon}r$) 4.6, dielectric substance height(H) 30 Mills, and 2.68 Mills(2 oz) of copper plate thickness(T). Experiment result satisfied specification of amplifier with gains are 57.03 dB in 2.11 ~ 2.17 GHz, 3GPP frequency band, PEP output is 50.30 dBm, W-CDMA average power is 47.01 dBm, and ACLR characteristics at 5MHz offset frequency band station is -40.45 dBc. Especially, 3-way DCHD power amplifier showed excellence efficiency performance improvement in same ACLR than general doherty power amplifier.

• Journal of the Institute of Electronics Engineers of Korea SD
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• v.41 no.12
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• pp.59-65
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• 2004

A stable reference voltage generator is necessary to the infrared image signal readout circuit(ROIC) to improve noise characteristics of signal originated from infrared devices, that is, to gain good images. In this paper, bandgap circuit operating at cryogenic temperature of 77K for Infrared image ROIC(readout integrated circuit) was first made. It demonstrates practical use possibility through taking measurements and estimations. Bandgap circuit is a representative voltage reference circuit. Most of bandgap reference circuits which are presented so far operate at room temperature, and their characteristic are not suitable for infrared image ROIC operating at liquid nitrogen temperature, 77K. To design bandgap circuit operating at cryogenic temperature, suitable circuit is selected and the parameter characteristics of used devices as temperature change are seen by a theoretical study and fitted at liquid temperature with considering such characteristics. This circuit has been fabricated in the Hynix 0.6um standard CMOS process, and the output voltage measured shows that the stability is 1.042±0.0015V over the temperature range of 60K to 110K and is better than bandgap circuits operated at room temperature.

• Journal of the Institute of Electronics Engineers of Korea SC
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• v.39 no.4
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• pp.16-24
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• 2002

This work describes a 10b 120 MSample/s CMOS pipelined A/D converter(ADC) based on a merged-capacitor switching(MCS) technique for high signal processing speed and high resolution. The proposed ADC adopts a typical multi-step pipelined architecture to optimize sampling rate, resolution, and chip area, and employs a MCS technique which improves sampling rate and resolution reducing the number of unit capacitor used in the multiplying digital-to-analog converter (MDAC). The proposed ADC is designed and implemented in a 0.25 um double-poly five-metal n-well CMOS technology. The measured differential and integral nonlinearities are within ${\pm}$0.40 LSB and ${\pm}$0.48 LSB, respectively. The prototype silicon exhibits the signal-to-noise-and-distortion ratio(SNDR) of 58 dB and 53 dB at 100 MSample/s and 120 MSample/s, respectively. The ADC maintains SNDR over 54 dB and the spurious-free dynamic range(SFDR) over 68 dB for input frequencies up to the Nyquist frequency at 100 MSample/s. The active chip area is 3.6 $mm^2$(＝ 1.8 mm ${\times}$ 2.0 mm) and the chip consumes 208 mW at 120 MSample/s.

• Journal of the Institute of Electronics Engineers of Korea SD
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• v.47 no.4
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• pp.75-87
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• 2010

For two input-protection schemes suitable for RF ICs utilizing the thyristor and diode protection devices, which can be fabricated in standard CMOS processes, we attempt an in-depth comparison on HBM ESD robustness in terms of lattice heating inside protection devices and peak voltages developed across gate oxides in input buffers, based on DC, mixed-mode transient, and AC analyses utilizing a 2-dimensional device simulator. For this purpose, we construct an equivalent circuit for an input HBM test environment of a CMOS chip equipped with the input ESD protection circuits, which allows mixed-mode transient simulations for various HBM test modes. By executing mixed-mode simulations including up to six active protection devices in a circuit, we attempt a detailed analysis on the problems, which can occur in real tests. In the procedure, we suggest to a recipe to ease the bipolar trigger in the protection devices and figure out that oxide failure in internal circuits is determined by the junction breakdown voltage of the NMOS structure residing in the protection devices. We explain the characteristic differences of two protection schemes as an input ESD protection circuit for RF ICs, and suggest valuable guidelines relating design of the protection devices and circuits.

• Journal of the Institute of Electronics Engineers of Korea SD
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• v.45 no.2
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• pp.118-124
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• 2008

For forward error correction, DVB-S2, which is the digital video broadcasting forward error coding and modulation standard for satellite television, uses a system based the concatenation of BCH with LDPC inner coding. In DVB-S2 the LDPC codes are defined for 11 different code rates, which means that a DVB-S2 LDPC decoder should support multiple code rates. Seven of the 11 code rates, 3/5, 2/3, 3/4, 4/5, 5/6, 8/9, and 9/10, are regular and the rest four code rates, 1/4, 1/3, 2/5, and 1/2, are irregular. In this paper we propose a flexible decoder for the regular LDPC codes. We combined the partially parallel decoding architecture that has the advantages in the chip size, the memory efficiency, and the processing rate with Benes network to implement a DVB-S2 LDPC decoder that can support multiple code rates with a block size of 64,800 and can configure the interconnection between the variable nodes and the check nodes according to the parity-check matrix. The proposed decoder runs correctly at the frequency of 200MHz enabling 193.2Mbps decoding throughput. The area of the proposed decoder is $16.261m^2$ and the power dissipation is 198mW at a power supply voltage of 1.5V.

• Journal of the Korea Academia-Industrial cooperation Society
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• v.15 no.8
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• pp.4815-4820
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• 2014

As semiconductor chips are on a small scale, large content and high integratation, it is essential to develop the device of pick and place at the system of the semiconductor test handler to ensure its high precision and durability. In this study, inspection equipment frame model of a semiconductor test handler picker was investigated by vibration analysis with the property of the natural frequency and harmonic response. As 3 kinds of analysis case models, the device of pick and place was located at the left side (Case 1), the center (Case 2) and the right side (Case 3) of the upper guideline. The range of natural frequencies until the 6th order on this frame model ranges from 80Hz to 500Hz. As the analysis of the harmonic response when the frame is resonant, Case 2 showed the maximum equivalent stress of 52.802 MPa more than Cases 1 or 3. Case 2 was the most intensive among the three cases. Using the analysis result of this study, the design of the frame model, which can be applied to the safe working environment of the system is believed to be possible.

• Proceedings of the Korean Vacuum Society Conference
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• 2013.02a
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• pp.361-361
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• 2013

비냉각 적외선 검출소자는 빛이 전혀 없는 환경에서도 사물을 감지하는 열상장비의 핵심소자이다. 마이크로볼로미터 적외선 검출기는 상온에서 동작하며, 온도안정화를 위해 TEC를 장착하여 진공패키지로 조립된다. 패키지는 진공을 유지할 수 있도록 일반적으로 메탈로 제작되며, 단가 감소 및 생산성 증대를 위해 wafer level packaging 방법을 이용한다. 마이크로볼로미터의 특성은 패키지의 진공 변화에 매우 민감하다. 센서의 감도를 증가시키기 위해서는 진공환경을 유지해야 한다. 볼로미터 소자의 특성은 상압에서 열전도는 기판과 멤브레인 사이의 에어갭을 통해 열손실을 야기하므로 센서의 반응도가 현저히 줄어든다. 에어갭이 1 um 정도 되더라도 그 사이에 존재하는 열전도가 가능하므로 진공을 유지하여 열고립 상태를 증대시킬 수 있다. 이에 본 연구에서는 소자의 동작시 압력, 즉 진공도가 볼로미터 소자의 반응도 특성에 미치는 영향을 조사하였다. 마이크로볼로미터 소자는 $2{\times}8$ 어레이 형태로 제작하였으며, metal pad를 각 단위셀에 배치하였으며, 공통전극으로 한 개의 metal pad를 넣어 설계하였다. 흡수체로써 VOx를 사용하였으며, 열 고립구조를 위해 2.5 um 공명 흡수층의 floating 구조로 멤브레인을 형성하였다. 진공패키지는 메탈패키지를 제작하여 볼로미터 칩을 TEC 위에 장착하였으며, 신호의 감지를 위해 가변저항을 매칭시켰다. 반응도는 신호 대 잡음 값을 획득하여 소자에 도달하는 적외선 에너지에 대해 반응하는 값을 계산에 의해 얻어내는 것이다. 픽셀 크기는 $50{\times}50$ um이며, 패키지 조립 공정 후 온도변화에 따른 저항 측정을 통해 TCR 값을 얻었다. 이때 TCR은 약 -2.5%/K으로 나타났다. $2{\times}8$의 4개 단위소자에 대해 측정한 값은 균일하게 TCR 값이 나타났다. 광반응 특성은 볼로미터 단위소자에 대해서 먼저 고진공(5e-6 torr) 하에서 측정하였으며, 반응도는 25,000 V/W의 값을 나타내었고, 탐지도는 약 2e+8 $cmHz_{1/2}$/W로 나타났다. 패키지의 압력 조절을 위해 TMP 및 로터리 펌프를 이용하여 100 torr에서 1e-4 torr의 범위에서 압력조절 밸브를 이용하여 질소가스의 압력으로 진공도를 변화시켰다. 적외선 반응신호는 압력이 증가함에 따라 감소하였으며, 2e-1 torr의 압력에서 신호의 크기가 감소하기 시작하여 5 torr에서 반응도의 1/2 값을 나타냄을 알 수 있었다. 30 torr 이상에서는 신호가 잡음값 과거의 동일하여 신호대 잡음비가 1로 나타남을 알 수 있었다. 또한 진공도 변화에 대해, 흑체온도에 따른 반응도 및 탐지도의 특성을 조사한 결과를 발표한다. 반응도의 증가를 위해 진공도는 진공도는 1e-2 torr 이하의 압력을 유지해야 함을 본 실험을 통해 알 수 있었다.

• The KIPS Transactions:PartD
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• v.10D no.6
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• pp.1059-1066
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• 2003

In this paper, the magnetic sensing system is designed and implemented for the safe security in internet commerce system. When the payment is required inthe internet commerce system, the magnetic sensing system will get the information from a credit card without keyboard input and then encrypt and transmit the information to server. The credit card sensing system, which is proposed in this paper, is safe from keyboard hacking because it encrypts card information immediately in its internal chip and sends the information to host system. For the protection of information, the magnetic sensing system is basically based on a synchronous stream cipher cryptosystem which is related to a group of matrices. The size of matrices and the bits of keys for the best performances are determined for various cases. It is shown that for credit card payments. matrices of size 2 have good performance even at most 128bits keys with the consideration of inverse matrices. For authentication of general-purpose data, the magnetic sensing system needs more than 1.5KB data and in this case, the optimum size of matrices is 2 or 3 at more 256bits keys with consideration of inverse matrices.

• Journal of the Institute of Electronics Engineers of Korea SD
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• v.41 no.10
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• pp.95-104
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• 2004

This paper propose a motion estimator architecture to reduce the power consumption of the most-power-consuming motion estimation method when designing multimedia SoC with deep submicron technologies below 0.13${\mu}{\textrm}{m}$. The proposed architecture considers both dynamic and static power consumption so that it is suitable for large leakage process technologies, while conventional architectures consider only dynamic power consumption. Consequently, it is suitable for mobile information terminals such as mobile videophone where efficient power management is essential. It exploits full search method for simple hardware implementation. It also exploits early break-off method to reduce dynamic power consumption. To reduce static power consumption, megablock shutdown method considering power line noise is also employed. To evaluate the proposed architecture when applied multimedia SoC, system-level control flow and low-power control algorithm are developed and the power consumption was calculated based on thor From the simulation results, power consumption was reduced to about 60%. Considering the line width reduction and increased leakage current due to heat dissipation in chip core, the proposed architecture shows steady power reduction while it goes worse in conventional architectures.

• Journal of the Institute of Electronics Engineers of Korea SD
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• v.43 no.6 s.348
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• pp.47-52
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• 2006

This paper proposes a novel low-power $32bit\times32bit$ multiplier for deep submicron technologies beyond 130nm. As technology becomes small, static power due to leakage current significantly increases, and it becomes comparable to dynamic power. Recently, shutdown method based on MTCMOS is widely used to reduce both dynamic and static power. However, it suffers from severe power line noise when restoring whole large-size functional block. Therefore, the proposed multiplier mitigates this noise by shutting down and waking up sequentially along with pipeline stage. Fabricated chip measurement results in $0.35{\mu}m$ technology and gate-transition-level simulation results in 130nm and 90nm technologies show that it consumes $66{\mu}W,\;13{\mu}W,\;and\;6{\mu}W$ in idle mode, respectively, and it reduces power consumption to $0.04%\sim0.08%$ of active mode. As technology becomes small, power reduction efficiency degrades in the conventional clock gating scheme, but the proposed multiplier does not.