• The Journal of Korean Institute of Electromagnetic Engineering and Science
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• v.28 no.10
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• pp.769-778
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• 2017

In this paper, a self-interference signal cancellation(SIC) circult for In-band Full-Duplex has been developed and tested in RF/analog region. By use of this SIC circuit, a FM two-way radio has been developed working at FRS(Family Radio Service) band. The two-way radio device is transmitting the FM modulated signal and demodulating the wanted FM signal at the same time. A circulator is used to enable a single antenna to transmit and receive simuultaenously. The receiver circuit needs to cancel out the self-interference signal due to the transmit signal. A vector modulator(VM) is used to control the phase and magnitude of the esitmated signal. And in-phase and quadrature correlators are used to figure out the optimal coefficients of the VM to remove the self-interference signal according to the change of channel environment. In this work, SA58646 has been used as the FM transceiver, and the system is tested with a frequency of 465 MHz and a bandwidth of 12.5 kHz FM signal. The output power is 17.2 dBm at the antenna port, and the self intererence signal level is measured -49.2 dBm at the receiver end. Therefore the SIC level is measured by 66.4 dB.

• Journal of the Korea Institute of Information and Communication Engineering
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• v.9 no.4
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• pp.824-831
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• 2005

Past corporaion's network security system is single security solution, or mixed several ways, but there was inefficient system because doing not get into organic link But, constructed more strong security system by ESM enterance on. ESM uses way to integrate of each agent to manage easily various kinds security solution. That is, it is system that connect system of existent VPN, FireWall, IDS and so on configurationally depending on security policy and manage. ESM is security system that is developed more than existent security system. But, practical use of network and the development speed of technology being increasing with the mon faster speed, is heightening the level more as well as dysfunction of information crime and so on. Many improvements are required at ESM system, this research wished to make up for the weak-point in the ESM system about interior security. Studied on structure of security solution that is basis of security policy. VPN, Firewall, IDS's link that is main composition of existing security system analysis, reconstructed. And supplemented security of ESM system itself. Establish imaginary intrusion and comparative analysis access data that apply each Telnet Log analysys IDS existent ESM system and proposed ESM system comparative analysis. Confirm the importance of interior security and inspected security of proposed system.

• Journal of Sensor Science and Technology
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• v.7 no.1
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• pp.31-38
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• 1998

Multi-channel sensors can be used to increase the reliability and remove the random iloise in ion-sensitive field effect transistors(ISFETs). Multi-channel sensors is also an essential step toward potential fabrication of sensors for several ionic species in one device. However, when the multi-channel sensors are separately biased, the biasing problems become difficult, that is to say, the bias circuit is needed as many sensors. In this work, a circuit for biasing the four pH-ISFETs in null-balance method, where bias voltages are switched, was proposed. The proposed concept is need only one bias circuit for the four sensors. Therefore it has advantages of smaller size and lower power consumption than the case that all sensors are separately biased at a time. The proposed circuit was tested with discrete devices and its performance was investigated. In the recent trend, sensor systems are implemented as portable systems. So the verified measurement circuit was integrated by using the CMOS circuit. Fortunately, ISFET fabrication process can be compatible with CMOS process. Full circuit has a mask area of $660{\mu}m{\times}500{\mu}m$. In the future, this step will be used for developing the smart sensor system with ISFET.

• The Journal of Korean Institute of Communications and Information Sciences
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• v.42 no.4
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• pp.864-870
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• 2017

This paper describes a Dual Buck Converter with mode control using variable Frequency to Voltage for portable devices requiring wide load current. The inherent problems of PLL compensation and efficiency degradation in light load current that the conventional hysteretic buck converter has faced have been resolved by using the proposed Dual buck converter which include improved PFM Mode not to require compensation. The proposed mode controller can also improve the difficulty of detecting the load change of the mode controller, which is the main circuit of the conventional dual mode buck converter, and the slow mode switching speed. the proposed mode controller has mode switching time of at least 1.5us. The proposed DC-DC buck converter was implemented by using $0.18{\mu}m$ CMOS process and die size was $1.38mm{\times}1.37mm$. The post simulation results with inductor and capacitor including parasitic elements showed that the proposed circuit received the input of 2.7~3.3V and generated output of 1.2V with the output ripple voltage had the PFM mode of 65mV and 16mV at the fixed switching frequency of 2MHz in hysteretic mode under load currents of 1~500mA. The maximum efficiency of the proposed dual-mode buck converter is 95% at 80mA and is more than 85% efficient under load currents of 1~500mA.

• Journal of the Institute of Electronics Engineers of Korea SP
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• v.44 no.5
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• pp.103-111
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• 2007

In this paper, we propose a VLSI architecture of hardware optimized high quality image signal processor for a Single-chip CMOS Image Sensor(CIS). The Single-chip CIS is usually used for mobile applications, so it has to be implemented as small as possible while maintaining the image quality. Several image processing algorithms are used in ISP to improve captured image quality. Among the several image processing blocks, demosaicing and image filter are the core blocks in ISP. These blocks need line memories, but the number of line memories is limited in a low cost Single-chip CIS. In our design, high quality edge-adaptive and cross channel correlation considered demosaicing algorithm is adopted. To minimize the number of required line memories for image filter, we share the line memories using the characteristics of demosaicing algorithm which consider the cross correlation. Based on the proposed method, we can achieve both high quality and low hardware complexity with a small number of line memories. The proposed method was implemented and verified successfully using verilog HDL and FPGA. It was synthesized to gate-level circuits using 0.25um CMOS standard cell library. The total logic gate count is 37K, and seven and half line memories are used.

• Journal of the Institute of Electronics Engineers of Korea SD
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• v.39 no.11
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• pp.14-23
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• 2002

Two implementation methods for SOVA (Soft Output Viterbi Algorithm)of Turbo decoder are applied and verfied. The first method is the combination of a trace back (TB) logic for the survivor state and a double trace back logic for the weight value in two-step SOVA. This architecure of two-setp SOVA decoder allows important savings in area and high-speed processing compared with that of one-step SOVA decoding using register exchange (RE) or trace-back (TB) method. Second method is adjusting the reliability value with a scaling factor between 0.25 and 0.33 in order to compensate for the distortion for a rate 1/3 and 8-state SOVA decoder with a 256-bit frame size. The proposed schemes contributed to higher SNR performance by 2dB at the BER 10E-4 than that of SOVA decoder without a scaling factor. In order to verify the suggested schemes, the SOVA decoder is testd using Xillinx XCV 1000E FPGA, which runs at 33.6MHz of the maximum speed with 845 latencies and it features 175K gates in the case of 256-bit frame size.

• Journal of the Institute of Electronics Engineers of Korea SD
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• v.39 no.9
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• pp.11-18
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• 2002

This paper presents a CPW phase shifter and shunt stub with air-bridge on a 10-${\mu}m$-thick oxidized porous silicon(OPS) substrate using surface micromachining. The line dimensions of the CPW phase shifter was designed with S-W-Sg = 100-30-400 ${\mu}m$. And the width and length of the air-bridge with "ㄷ“ shape were 100 ${\mu}m$ and 400-460-400 ${\mu}m$, respectively. In order to achieve low attenuation, stepped air-bridge CPW phase shift was proposed. The insertion loss of the stepped air-bridge CPW phase shift is more improved than that of no stepped air-bridge CPW phase shift. The measured phase characteristic of the fabricated CPW phase shifter is close to 180$^{\circ}$ over a very broad frequency range of 28 GHz. The measured working frequency of short-end series stub is 28.7 GHz and the return loss is - 20 dB. And the measured working frequency of short-end shunt stub is 28.9 GHz and the return loss is - 23 dB at midband. As a result, the pattering of stub in the center conductor of CPW lines can offer size reduction and lead to high density chip layouts.

• The Journal of Korean Institute of Communications and Information Sciences
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• v.28 no.10C
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• pp.967-983
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• 2003

In wireless spread-spectrum communication systems utilizing PN (pseudo noise) sequences, a variety of noise sources from the channel affect the data reception performance. Among them, in this paper we are concerned with the narrowband interference that may arise from the use of the spectral bands overlapped by the existing narrowband users or the intentional jammers as in military communication. The effect of this interference can be reduced to some extent at the receiver with the PN demodulation by processing gain. It is known, however, that when the interferers are strong, the reduction cannot be sufficient and thereby requiring the extra use of narrowband interference cancellers (NIC's) at the receivers. A class of adaptive NIC's are studied here based on different two cost functions. One is the chip mean-squared error (MSE) computed prior to the PN demodulation and used in the conventional cancellers. Since thses conventional cancellers should be operated at the chip rate, the computational requirements are enormous. The other is the symbol MSE computed after the PN demodulation in which case the weights of the NIC's can be updated at a lot lower symbol rate. To compare the performance of these NIC's, we derive a common measure of performance, i.e., the symbol MSE after the PN demodulation. The analytical results are verified by computer simulation. As a result, it is shown that the cancellation capability of the symbol-rate NIC's are similar or better than the conventional one while the computational complexity can be reduced a lot.

• Journal of the Microelectronics and Packaging Society
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• v.6 no.2
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• pp.37-43
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• 1999

Modules of the system that requires large capacity and high-speed information processing are implemented in the form of MCM that allows high-speed data processing, high density circuit integration and widely applied to such fields as ATM, GPS and PCS. Hence we developed the ATM switching module that is consisted of three chips and 2.48 Gbps data throughput, in the form of 10 multi-layer by Cu/Photo-BCB and 491pin PBGA which size is $48 \times 48 \textrm {mm}^2$. hnologies required for the development of the MCM includes extracting parameters for designing the substrate/package through the interconnect characterization to implement the high-speed characteristics, thermal management at the high-density MCM, and the generation of the testability that is one of the most difficult issues for developing the MCM. For the development of the ATM Switching MCM, we extracted signaling delay, via characteristics and crosstalk parameters through the interconnect characterization on the MCM-D. For the thermal management of 15.6 Watt under the high-density structure, we carried out the thermal analysis. formed 1.108 thermal vias through the substrate, and performed heat-proofing processing for the entire package so that it can keep the temperature less than $85^{\circ}C$. Lastly, in order to ensure the testability, we verified the substrate through fine pitch probing and applied the Boundary Scan Test (BST) for verifying the complex packaging/assembling processes, through which we developed an efficient and cost-effective product.

• The Journal of Korea Institute of Information, Electronics, and Communication Technology
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• v.10 no.2
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• pp.168-175
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• 2017

In this paper, a 5V small-area NMOS-diode eFuse OTP memory cell is proposed. This cell which is used in PMICs consists of a 5V NMOS transistor and an eFuse link as a memory part, based on a BCD process. Also, a regulated voltage of V2V ($=2.0V{\pm}10%$) instead of the conventional VDD is used to the pull-up loads of a VREF circuit and a BL S/A circuit to obtain a wider operational voltage range of the eFuse memory cell. When this proposed cells are used in the simulation, their sensing resistances are found to be $15.9k{\Omega}$ and $32.9k{\Omega}$, in the normal read mode and in the program-verify-read mode, respectively. Furthermore, the read current flowing through a non-blown eFuse is restricted to $97.7{\mu}A$. Thus, the eFuse link of a non-blown eFuse OTP memory cell is kept non-blown. The layout area of the designed 1kb eFuse OTP memory IP based on Dongbu HiTek's BCD process is $168.39{\mu}m{\times}479.45{\mu}m(=0.08mm^2)$.