• The Journal of the Korea Contents Association
• /
• v.4 no.4
• /
• pp.123-131
• /
• 2004

Internet is absolutely contributed to information technology revolution nowadays. Internet services such as voice and data, etc. are provided home or small office via home gateway. The development of communication equipment via home gateway is implemented rapidly, and its product various. This paper presents the design and implementation of the VoIP equipment including the telephone function based on the embedded environment and being connected to the home gateway and the PC because of taking 2-ethernet LAN ports. As developing environment, the STLC1502 developed at ST Microelectronics as single chip solution, VxWorks as RTOS, and C language as coding mechanism are used. The verification of the developed systems for the voice test is carried out for the gatekeeper via Internet. The performance parameter is considered as the call processing capacity measuring the time of the call setup and clearing, and the data processing capacity for the file transfer. As a call setup and clearing is about 95ms, the call processing capacity is about 10 calls per second. The data processing capacity is 5.7Mbps in case of file transfer of server and client environment. Therefore the performance result is satisfied in the aspect of the call processing time and the data transfer time in Internet.

• Journal of the Institute of Electronics and Information Engineers
• /
• v.51 no.10
• /
• pp.80-86
• /
• 2014

A low-noise readout circuit is studied for 2-D capacitive microbolometer focal plane arrays (FPAs). In spite of the merits of the integration method, a simple and effective pixelwise readout circuit without integration is used for input circuit because of a small pixel size and narrow noise bandwidth. To reduce the power consumption and the kT/C noise, which is the dominant noise of the capacitive microbolometer FPAs with small capacitance, a new correlated double sampling (CDS) is used for columnwise circuit. The proposed circuit has been designed using a $0.35-{\mu}m$ 2-poly 4-metal CMOS process for a microbolometer array with a pixel size of $50{\mu}m{\times}50{\mu}m$. The proposed circuit effectively reduces the kT/C noise and the other low-frequency noise of microbolometer, and the noise characteristics of the fabricated chip have been verified by measurements. The rms noise voltage of the proposed circuit is reduced from 30 % to 55 % compared to that of the simple readout input circuit, and the noise equivalent temperature difference (NETD) of the proposed circuit is very low value of 21.5 mK.

• Journal of the Korean Institute of Telematics and Electronics D
• /
• v.35D no.10
• /
• pp.39-50
• /
• 1998

Wide-band sharp-transition filters are widely used in applications such as wireless CODEC design or medical systems. Since these filters suffer from large sensitivity and roundoff noise, large word-length is required for the VLSI implementation, which increases the hardware size and the power consumption of the chip. In this paper, a low-power implementation technique for digital filters with wide-band sharp-transition characteristics is proposed using CPL (Complementary Pass-Transistor Logic), LWDF (Lattice Wave Digital Filter) and a modified DIFIR (Decomposed & Interpolated FIR) algorithm. To reduce the short-circuit current component in CPL circuits due to threshold voltage reduction through the pass transistor, three different approaches can be used: cross-coupled PMOS latch, PMOS body biasing and weak PMOS latch. Of the three, the cross-coupled PMOS latch approach is the most realistic solution when the noise margin as well as the energy-delay product is considered. To optimize CPL transistor size with insight, the empirical formulas for the delay and energy consumption in the basic structure of CPL circuits were derived from the simulation results. In addition, the filter coefficients are encoded using CSD (Canonic Signed Digit) format and optimized by a coefficient quantization program. The hardware cost is minimized further by a modified DIFIR algorithm. Simulation result shows that the proposed method can achieve about 38% reductions in power consumption compared with the conventional method.

• Korean Journal of Optics and Photonics
• /
• v.5 no.3
• /
• pp.423-430
• /
• 1994

We designed and fabricated the single mode fiber pigtailed DFB-LD module for 2.5 Gbps optical communication system. In the design of the DFB-LD module, we made the module divided into two parts of inner sub-module and outer 14-pin butterfly package and cylindrical shaped sub-module contain quasi confocal 2 lens system including optical isolator and electrical connection between these parts via hybrid substrate of bias T circuit. Laser welding was used to assemble the sub-module which requires accurate fixing between optical elements. The fabricated DFB-LD module showed optical coupling efficiency of 20% and - 3 dB small signal response of more than 2.6 GHz. We confirmed mechanical reliability of the module by temperature cycle test where the tested module exhibit optical power fluctuation of less than 10%. Finally we evaluated the performance of the fabricated DFB-LD module as light source of 2.5 Gbps optical communication system, sensitivity of - 30.2 dBm was obtained through 47 km optical fiber transmission under the criterion of $1\times10^{-10}$ BER and transmission penalties were 1.5 dB caused by extinction ratio and 1.0 dB caused by chromatic dispersion of normal single mode fiber. fiber.

• Journal of the Institute of Electronics Engineers of Korea TC
• /
• v.41 no.12
• /
• pp.103-108
• /
• 2004

In this paper, we present MIMIC(Millimeter-wave Monolithic Integrated Circuit) up-mixer with low conversion loss and low LO power for the V-band transmitter applications. The up-mixer was successfully integrated by using 0.1 ㎛ GaAs pseudomorphic HEMTs(PHEMTs) and coplanar waveguide (CPW) structures. The circuit is designed to operate at RF frequencies of 60.4 GHz, IF frequencies of 2.4 GHz, and LO frequencies of 58 GHz. The fabricated MIMIC up-mixer size is 2.3 mmxl.6 mm. The measured results show that the low conversion loss of 1.25 dB when input signal is -10.25 dBm at LO power of 5.4 dBm. The LO to RF isolation is 13.2 dB at 58 GHz. The fabricated V-band up-mixer represents lower LO input power and conversion loss characteristics than previous reported millimeter-wave up-mixers.

• Journal of the Institute of Electronics Engineers of Korea SD
• /
• v.47 no.3
• /
• pp.28-34
• /
• 2010

In this paper, the transceiver for RFID reader using 13.56MHz as a carrier frequency and meeting International Standard ISO 14443 type A, 14443 type B and 15693 is presented. The receiver is composed of envelope detector, VGA(Variable Gain Amplifier), filter, comparator to recovery the received signal. The proposed automatic reference voltage generator, positive peak detector, negative peak detector, and data slicer circuit can adjust the decision level of reference voltage over the received signal amplitudes. The transmitter is designed to drive high voltage and current to meet the 15693 specification. By using inductor loading circuit which can swing more than power supply and drive large current even under low impedance condition, it can control modulation rate from 30 percent to 5 percent, 100 perccnt and drive the output currents from 5 mA to 240 mA depending on standards. The 13.56 MHZ RFID reader is implemented in $0.18\;{\mu}m$ CM08 technology at 3.3V single supply. The chip area excluding pads is $1.5mm\;{\times}\;1.5mm$.

• The Journal of Korean Institute of Electromagnetic Engineering and Science
• /
• v.21 no.4
• /
• pp.362-370
• /
• 2010

In this paper, a compact RF Front-end module for Wireless Fidelity(Wi-Fi) and Worldwide Interoperability for Microwave Access(WiMAX) applications is realized by low temperature co-fired ceramic(LTCC) technology. The RF Front-end module is composed of three LTCC band-pass filters, a Film Bulk Acoustic Resonator(FBAR) filter, fully embedded matching circuits, an SPDT switch for mode selection, an SPDT switch for Tx/Rx selection, and an SP4T switch for band selection. The parasitic elements of 0.2~0.3 pF are generated by the structure of stacking in the top pad pattern for DC block capacitor of SPDT switch for mode selection. These kinds of parasitic elements break the matching characteristic, and thus, the overall electrical performance of the module is degraded. In order to compensate it, we insert a parallel lumped-element inductor on capacitor pad pattern for DC block, so that we obtain the optimized performance of the RF Front-end module. The fabricated RF front-end module has 12 layers including three inner grounds and it occupies less than $6.0mm{\times}6.0mm{\times}0.728mm$.

• The Journal of Korean Institute of Electromagnetic Engineering and Science
• /
• v.28 no.10
• /
• pp.769-778
• /
• 2017

In this paper, a self-interference signal cancellation(SIC) circult for In-band Full-Duplex has been developed and tested in RF/analog region. By use of this SIC circuit, a FM two-way radio has been developed working at FRS(Family Radio Service) band. The two-way radio device is transmitting the FM modulated signal and demodulating the wanted FM signal at the same time. A circulator is used to enable a single antenna to transmit and receive simuultaenously. The receiver circuit needs to cancel out the self-interference signal due to the transmit signal. A vector modulator(VM) is used to control the phase and magnitude of the esitmated signal. And in-phase and quadrature correlators are used to figure out the optimal coefficients of the VM to remove the self-interference signal according to the change of channel environment. In this work, SA58646 has been used as the FM transceiver, and the system is tested with a frequency of 465 MHz and a bandwidth of 12.5 kHz FM signal. The output power is 17.2 dBm at the antenna port, and the self intererence signal level is measured -49.2 dBm at the receiver end. Therefore the SIC level is measured by 66.4 dB.

• Journal of the Korea Institute of Information and Communication Engineering
• /
• v.9 no.4
• /
• pp.824-831
• /
• 2005

Past corporaion's network security system is single security solution, or mixed several ways, but there was inefficient system because doing not get into organic link But, constructed more strong security system by ESM enterance on. ESM uses way to integrate of each agent to manage easily various kinds security solution. That is, it is system that connect system of existent VPN, FireWall, IDS and so on configurationally depending on security policy and manage. ESM is security system that is developed more than existent security system. But, practical use of network and the development speed of technology being increasing with the mon faster speed, is heightening the level more as well as dysfunction of information crime and so on. Many improvements are required at ESM system, this research wished to make up for the weak-point in the ESM system about interior security. Studied on structure of security solution that is basis of security policy. VPN, Firewall, IDS's link that is main composition of existing security system analysis, reconstructed. And supplemented security of ESM system itself. Establish imaginary intrusion and comparative analysis access data that apply each Telnet Log analysys IDS existent ESM system and proposed ESM system comparative analysis. Confirm the importance of interior security and inspected security of proposed system.

• Journal of Sensor Science and Technology
• /
• v.7 no.1
• /
• pp.31-38
• /
• 1998

Multi-channel sensors can be used to increase the reliability and remove the random iloise in ion-sensitive field effect transistors(ISFETs). Multi-channel sensors is also an essential step toward potential fabrication of sensors for several ionic species in one device. However, when the multi-channel sensors are separately biased, the biasing problems become difficult, that is to say, the bias circuit is needed as many sensors. In this work, a circuit for biasing the four pH-ISFETs in null-balance method, where bias voltages are switched, was proposed. The proposed concept is need only one bias circuit for the four sensors. Therefore it has advantages of smaller size and lower power consumption than the case that all sensors are separately biased at a time. The proposed circuit was tested with discrete devices and its performance was investigated. In the recent trend, sensor systems are implemented as portable systems. So the verified measurement circuit was integrated by using the CMOS circuit. Fortunately, ISFET fabrication process can be compatible with CMOS process. Full circuit has a mask area of $660{\mu}m{\times}500{\mu}m$. In the future, this step will be used for developing the smart sensor system with ISFET.