• Proceedings of the Korean Society for Agricultural Machinery Conference
• /
• 2002.02a
• /
• pp.192-197
• /
• 2002

1. 실시간 모니터링 -온실 내부환경의 계측장치로 모듈화된 단일 칩 마이크로프로세서를 이용한 하우스 모니터를 개발하였다. 개발된 다수의 하우스 모니터는 RS-485통신을 이용하여 개발된 프로토콜을 통하여 그룹 모니터와 통신하면서 계측 데이터를 전송하였고 안정된 계측 성능을 보였다. 또한 그룹 모니터는 하우스모니터로부터 수신한 데이터를 인터넷 환경 TCP/IP 통신에 의해 서버에 정보를 전송하고 데이터베이스 서버에 저장할 수 있었다. 2. 클라이언트 서버 모델 -클라이언트 모니터를 통하여 허용된 사용자들은 해당 온실의 상황을 원격지에서 파악할 수 있는 있었다. 또한 분산환경 기술을 이용하여 서버를 경유하여 데이터베이스 서버에서 데이터 셋을 가져와 과거 재배 사례 등을 조회 및 이용 가능하였다. 이는 전문가에게 접근을 허용함으로써 재배에 관한 지원이 가능하도록 하였다. 데이터 베이스 시스템으로 연계하여 온실환경 정보를 분석하는 것이 가능하였다. 3. 기대효과 및 나아가야 할 방향 -개발된 시스템을 식물 공장 내 작물의 재배환경을 데이터베이스화하여 재배사례 데이터베이스를 형성하고 작물이 가장 잘 자라는 최적 재배 환경을 연구하여 고품질의 작물 재배에 이용될 수 있다. 또한 식물공장의 운전실적, 환경 조건, 환경 조절비용 등의 분석에 효율적으로 이용될 수 있을 것으로 예상되며 각 환경인자들과의 관계를 구명하는데 도움을 줄 것이다. 축적된 작물의 재배 사례 데이터베이스를 이용하여 작물 특성 및 재배 연구에 도움을 줄 수 있을 것이다. 제어 장치들의 운영실적을 분석함으로써 제어 시스템의 효율적이고 경제적인 제어가 가능하도록 할 수 있을 것이다. 이들이 모두 완성되면 전문가 및 전문가 시스템으로부터 지원을 받는 지능형 식물공장이 가능할 것이다. 본 연구에서 개발한 계측 모듈 및 데이터베이스 시스템은 실제 농가에 설치된 전용선을 이용하여 실증 실험을 통해 수정·보완하여야 할 것이다. 또한 시설원예분야에서 있어서 통신체계에 대한 표준화 연구가 수행되어 앞으로 개발될 다른 시스템들과의 호환성을 갖도록 해야 할 것이다. 앞으로 온실의 경영 및 관리 데이터베이스를 개발하여 첨단온실의 통합 관리 및 정보 시스템을 구축하여야 할 것이다. 또한, 시설원예의 환경 설계의 기준을 적용할 수 있도록 하여야 할 것이다.

• Journal of KIISE
• /
• v.42 no.9
• /
• pp.1078-1089
• /
• 2015

In this paper, we propose the Min-hash Assisted Delta-compression Engine(MADE) to improve the lifetime of NAND flash-based storages at the device level. MADE effectively reduces the write traffic to NAND flash through the use of a novel delta compression scheme. The delta compression performance was optimized by introducing min-hash based LSH(Locality Sensitive Hash) and efficiently combining it with our delta compression method. We also developed a delta encoding technique that has functionality equivalent to deduplication and lossless compression. The results of our experiment show that MADE reduces the amount of data written on NAND flash by up to 90%, which is better than a simple combination of deduplication and lossless compression schemes by 12% on average.

• Journal of Korea Multimedia Society
• /
• v.16 no.1
• /
• pp.75-86
• /
• 2013

This paper presents a technique to implement embedded systems using interrupts of the one-chip microcontroller with many peripherals based on a multiple finite state machines model. The multiple finite state machine model utilizes the structure of FSMD used for hardware design and the features of flow control by interrupts. The main finite state machine corresponds to the main program and the sub-state machines corresponds to the interrupt subroutines. Therefore, interrupts from the peripherals can be processed immediately in the sub-state machines. The request and reply variables are used to interface between the finite state machines. Additional operating system is not necessary for the context switching between the main state machine and the sub-state machine, because the flow-control caused by interrupt can be replaced with the switching. An embedded system modeled on multiple finite state machine with ASM charts can be easily implemented by the conversion of ASM charts into C-language programs. This implementation technique can be easily adopted to the hardware oriented embedded systems because of the detail description of the model and the fast response to the interrupt events in the sub-state machine.

• Journal of the Institute of Convergence Signal Processing
• /
• v.7 no.4
• /
• pp.184-188
• /
• 2006

This paper presents DSP based narrow band satellite communication signal power detector for tracking control of mobile satellite antenna system. An analog filter based conventional power detector has poor performance due to frequency drift of carrier. Also, it is very difficult to change an analog filter bandwidth according to changed bandwidth of transmitted signal. To solve these difficulties, we proposed DSP based signal power detector, which is easy to change bandwidth of filter and to match shifted frequency of carrier. The proposed signal power detector consists of a FFT function to measure frequency drift of carrier, a programmable filter bank function to limit of received signal bandwidth and a power calculation function to measure power of filtered signal in 12-bit linear scale. Test results of implemented signal power detector, based on TMS320C5402 DSP, showed that it satisfied required functions and performances and properly operated.

• Journal of Convergence for Information Technology
• /
• v.11 no.9
• /
• pp.124-129
• /
• 2021

A time-interpolation technique has been applied to the conventional FLASH analog-to-digital converter (ADC) to increase a number of quantization level, thus it reduces not only a power dissipation, but also minimize an active chip area. In this work, we demonstrated 5-bit ADC which has 31 quantization levels consisting of 16 conventional voltage-mode comparators and 15 time-mode comparators. As a result, we have achieved about 48.4% voltage-mode comparator reductions. The ADC is fabricated in a 14nm fin Field-effect transistor (FinFET) process with an active die area of 0.0024 mm2 while consuming 0.82 mW through a 0.8 V supply. At 400-MS/s conversion rate, the ADC performs 28.03 dB SNDR (4.36 ENOB) at 21MHz input frequency.

• Journal of Advanced Navigation Technology
• /
• v.23 no.2
• /
• pp.207-213
• /
• 2019

Recently, the importance for internet of things (IoT) security has increased enormously and hardware-based compact chips are needed in IoT communication industries. In this paper, we propose low-complexity crypto-processor that unifies advanced encryption standard (AES), academy, research, institute, agency (ARIA), and CLEFIA protocols into one combined design. In the proposed crypto-processor, encryption and decryption processes are shared, and 128-bit round key generation process is combined. Moreover, the shared design has been minimized to be adapted in generic IoT devices and systems including lightweight IoT devices. The proposed crypto-processor was implemented in Verilog hardware description language (HDL) and synthesized to gate level circuit in 65nm CMOS process, which results in 11,080 gate counts. This demonstrates roughly 42% better than the aggregates of three algorithm implementations in the aspect of gate counts.

• Journal of the Microelectronics and Packaging Society
• /
• v.29 no.3
• /
• pp.31-35
• /
• 2022

Recently, with the 4th industrial revolution, the demand for high-density semiconductors for large-capacity data processing is increasing. Researchers are interested in researching the reliability of surface mount technology (SMT). In this study, the effect of PCB pad design on assembly and adhesion reliability of passive component was analyzed using design of experiment (DOE). The DOE method was established using the pad length, width, and distance between pads of the PCB as variables. The assembly defect rate of the passive element after the reflow process was derived according to the misplacement direction of the chip resistor. The shear force between the passive element and the PCB was measured using shear tests. In addition, the shape of the solder according to the pad design was analyzed through cross-sectional analysis.

• Journal of IKEEE
• /
• v.26 no.3
• /
• pp.373-379
• /
• 2022

In this paper, since the APD(Avalanche Photo Diode) for LTV(Light to Voltage) conversion uses a high voltage in the operating range unlike other PD(Photo Diode)s, the quenching resistor must be connected in series to prevent overcurrent when using the TIA(Transimpedance Amplifier). In such a case, quenching resistance may affect the transfer function of the TIA circuit, resulting in serious stability. Therefore, in this paper, by analyzing the effect of APD quenching resistance on the voltage and current loop transfer function of TIA, we propose a loop analysis and a method for determining the quenching resistance value to improve stability. TIA circuit with quenching resistance was designed by the proposed method and the stability of operation was verified through simulation and chip fabrication.

• Korean Journal of Optics and Photonics
• /
• v.33 no.3
• /
• pp.106-112
• /
• 2022

A two-dimensional optical code division multiple access (OCDMA) encoder/decoder, which is composed of add/drop filters and all-pass filters for delay operation, is proposed. An example design is presented, and its feasibility is illustrated through numerical simulations. The chip area of the proposed OCDMA encoder/decoder could be about one-third that of a previous OCDMA device employing delay waveguides. Its performance is numerically investigated using the transfer-matrix method combined with the fast Fourier transform. The autocorrelation peak level over the maximum cross-correlation level for incorrect wavelength hopping and spectral phase code combinations is greater than 3 at the center of the correctly decoded pulse, which assures a bit error rate lower than 10^-3, corresponding to the forward error-correction limit.

• Proceedings of the Korean Institute of Information and Commucation Sciences Conference
• /
• 2022.10a
• /
• pp.459-461
• /
• 2022

One of the big differences between Network-on-Chip (NoC) and the existing parallel processing system based on an off-chip network is that data packet routing is performed using a centralized control scheme. In such an environment, the best-effort packet routing problem becomes a real-time assignment problem in which data packet arriving time and processing time is the cost. In this paper, the Hungarian algorithm, a representative computational complexity reduction algorithm for the linear algebraic equation of the allocation problem, is implemented in the form of a hardware accelerator. As a result of logic synthesis using the TSMC 0.18um standard cell library, the area of the circuit designed through case analysis for the cost distribution is reduced by about 16% and the propagation delay of it is reduced by about 52%, compared to the circuit implementing the original operation sequence of the Hungarian algorithm.