• Journal of Digital Contents Society
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• v.9 no.3
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• pp.471-481
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• 2008

Test scheduling considering power dissipation is an effective technique to reduce the testing time of complex SoCs and to enhance fault coverage under limitation of allowed maximum power dissipation. In this paper, a modeling technique of test resources and a test scheduling algorithm for efficient test procedures are proposed and confirmed. For test resources modeling, two methods are described. One is to use the maximum point and next maximum point of power dissipation in test resources, the other one is to model test resources by partitioning of them. A novel heuristic test scheduling algorithm, using the extended-tree-growing-graph for generation of maximum embedded cores usable simultaneously by using relations between test resources and cores and power-dissipation-changing-graph for power optimization, is presented and compared with conventional algorithms to verify its efficiency.

• The Journal of Korean Institute of Communications and Information Sciences
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• v.28 no.6A
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• pp.379-385
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• 2003

In this paper, we propose a time constant control method for sieving local minimum problem of the multiuser detector using Hopfield neural network for synchronous multi-rate code division multiple access(CDMA) system in selective fading environments and its performance is compared with that of the parallel interference cancellation(PIC). We also assume that short scrambling codes of 256 chip length are used an uplink, suggest a simple correlation estimation algorithm and circuit complexity reduction method by using cyclostationarity property of short scrambling code.It is verified that multiuser detector using Hopfield neural network more efficiently cancels multiple access interference(MAI) and obtain better bit error rate and near-far resistant than conventional detector.

• The Journal of the Korea institute of electronic communication sciences
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• v.9 no.11
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• pp.1311-1316
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• 2014

To be used in a transmitter of a satellite transponder of this paper, X band 25W power amplifier module, a part constituting of high-power amplifier is transmitted to the equipment for transmitting to geostationary communications satellites(36,000Km distance). PAM consisted a total of four power amplifier module has a high output characteristic of the high-output amplifier is used in the ground station. Used in conjunction with the structured type power amplifier module is composed of Serial Combining Structure. This PAM(Power Amplifier Module) configured by combining the circuit with the power amplifier, 10 MMIC chips and the Al2O3 thin film substrate using a Hybrid Technique of power amplifier module, was implemented at X band PAM(Power Amplifier Module) of 25W grade.

• The Journal of the Korea institute of electronic communication sciences
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• v.3 no.3
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• pp.177-182
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• 2008

Because output of multi-code CDMA system adapted high speed data transmission becoming multi-level system use linear amplifier in output stage and complex output signal. Therefore, Multi-Code CDMA system has shortcoming of high price, high complexity etc. Binary CDMA technology that allow fetters in existing CDMA technology to supplement this shortcoming proposed. In binary CDMA system When correlator process high speed data, bottle-neck phenomenon is happened on synchronization acquisition process, it is very important parameter. Because existent correlator must there be advantage that power consumption is small but flow addition of several stages to receive correlation's value, the processing speed has disadvantage because the operation amount is much. Therefore in this paper, proposed correlator has characteristic such as data is able to high speed processing, chip area is independent and power consumption is constant in structure in binary CDMA system.

• Journal of the Microelectronics and Packaging Society
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• v.23 no.3
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• pp.1-6
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• 2016

The Internet of Things (IoT) is a new technology paradigm demanding one packaged system of various semiconductor and MEMS devices. Therefore, the development of electronic packaging technology with very high connectivity is essential for successful IoT applications. This paper discusses both fan-out wafer level packaging (FOWLP) and 3D stacking technologies to achieve the integrattion of heterogeneous devices for IoT. FOWLP has great advantages of high I/O density, high integration, and design flexibility, but ultra-fine pitch redistribution layer (RDL) and molding processes still remain as main challenges to resolve. 3D stacking is an emerging technology solving conventional packaging limits such as size, performance, cost, and scalability. Among various 3D stacking sequences wafer level via after bonding method will provide the highest connectivity with low cost. In addition substrates with ultra-thin thickness, ultra-fine pitch line/space, and low cost are required to improve system performance. The key substrate technologies are embedded trace, passive, and active substrates or ultra-thin coreless substrates.

• The Journal of Korea Institute of Information, Electronics, and Communication Technology
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• v.4 no.4
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• pp.286-294
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• 2011

Cable modems typically are implemented by a forward error correction(FEC) scheme. The ITU-T Recommendation J-38 Annex B specifies using 64- and 256- quadrature amplitude modulation (QAM) and extended RS coding scheme. In implementing the cable modem, there are some problems to fabricate and fitting on FPGA chip. First, many clocks are needed in implementing cable modem because of different code rate and different modulation types. To reduce the number of clocks, we use the two memories, which are different clock speed for reading and writing data. Second, this system lost the bit-synchronization and frame-synchronization in decoder, the system recognize that all data is error. This paper solves the problems by using simple 5-stage registers and unique sync-word. Based on solutions for about problems, the cable modem is fabricated on FPGA chip name as Vertex II pro xc2vp30-5 by Xilinx, and we confirmed the effectiveness of the results.

• Proceedings of the Korean Institute of Information and Commucation Sciences Conference
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• v.9 no.2
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• pp.119-122
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• 2005

RFID(Radio Frequency IDentification) is appearing by point technology by Ubiquitous environment of new paradigm and Logistics' application. But, RFID chip of this is high price and short bandwidth, low power and interference etc. can become technological problem. This is getting into obstacle in common use. Reader and tag, Embedded software etc.. that is accomplishing standardization is imported paying most expensive Royalty. This paper is RFID cognition system that use PDA in Ubiquitous environment to apply to Logistics system. RFID cognition system processes input/output of fundamental information attaching tag to Logistics of products. And RFID cognition system supports quick and correct and safe synthetic Logistics managerial system through construction of database. This can prove minimization and customer service of Logistics expense. RFID cognition system is advantage that can widen range of application to area that cognition system of existent fixing style can not do. Also, It can expect economical effect through inexpensive system construction.

• Journal of the Korea Institute of Information and Communication Engineering
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• v.18 no.3
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• pp.643-650
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• 2014

A hardware implementation of phase calculator for extracting 3D depth image from TOF(Time-Of-Flight) sensor is described. The designed phase calculator adopts redundant binary number systems and a pipelined architecture to improve throughput and speed. It performs arctangent operation using vectoring mode of DCORDIC(Differential COordinate Rotation DIgital Computer) algorithm. Fixed-point MATLAB simulations are carried out to determine the optimal bit-widths and number of iteration. The phase calculator has ben verified by FPGA-in-the-loop verification using MATLAB/Simulink. A test chip has been fabricated using a TSMC $0.18-{\mu}m$ CMOS process, and test results show that the chip functions correctly. It has 82,000 gates and the estimated throughput is 400 MS/s at 400Mhz@1.8V.

• Journal of the Korea Academia-Industrial cooperation Society
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• v.8 no.6
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• pp.1505-1512
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• 2007

The RFID Technology (which is importantly used at the Ubiquitous environment) is attached to all of the units like the ID cards and then information on the units and units' environment is transferred and processed through the radio frequency. so it is the no touched recognition system. RFID Technology's research of the middle ware and wireless interface etc. is currently conducted and variously broaden like the industry of the distribution and logistics. This paper suggests that the gate control system which is based on RFID middle ware is realized to prevent the district and facility for security. The indication of this paper is that algorithm (which is to certificate Users' enterance through RFID EPC code) is proposed and realizes the user certification module, the control module of the gates' opening and closing, the maintenance module of the gate, the display module of coming and going information, test program ect. through RFID technology.

• Journal of the Institute of Convergence Signal Processing
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• v.5 no.2
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• pp.165-171
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• 2004

Owing to small sizes and high density to the semiconductor It, it is difficult to discriminate the defects of ICs by human eyes. High precision inspection system with computer vision is essentially established for the manufacturing process due to the variety of defective parts. Especially it is difficult to implement the algorithm for the coplanarity of IC leads. Therefore in this paper, the inspection system which can detect the defects of the SOP types of ICs having 1cm${\times}$0.5cm of the chip size is implemented and evaluated it's performance. In order to optimally detect various items, some principles of geometry are theoretically presented , length measurement, pitch measurement, angle measurement, brightness of image and correcton of position. The interface circuit is designed for implementation of inspection system and connected the HANDLER. In the result, the system could detect two ICs' defects per second and confirmed the resolution of 20$\mu$m per pixel.