• Journal of the Institute of Convergence Signal Processing
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• v.11 no.3
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• pp.244-249
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• 2010

The design of error correction code with low complexity has a good attraction for next generation multi-level cell flash memory. Sharing sub-expressions is effective method to reduce complexity and chip size. This paper proposes a new design method of m-bit parallel BCH encoder based on serial linear feedback shift register structure with low complexity using sub-expression. In addition, general algorithm for obtaining the sub-expression is introduced. The sub-expression can be expressed by matrix operation between sub-matrix of generator matrix and sum of two different variables. The number of the sub-expression is restricted by. The obtained sub-expressions can be shared for implementation of different m-parallel BCH encoder. This paper is not focused on solving a problem (delay) induced by numerous fan-out, but complexity reduction, expecially the number of gates.

• Journal of the Korea Institute of Information and Communication Engineering
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• v.16 no.9
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• pp.2003-2008
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• 2012

A drive system is necessary to operate LED by an LED illumination system. Because Switched Mode Power Supply (SMPS) is higher in efficiency in the large capacity than Linear Regulator, it is used mainly and controls this in an analog form or digital method. A MCU and a DSP of the digital control central processing unit were higher in a unit price than existing analog control chip, so that an approach was not easy for application of SMPS. But it can take the earnings by it lets you integrate various digital control features like an LED illumination system in one MCU, and realizing a whole system. In this paper, we suggest the algorithm that can improve LED driving current in applying such a digital control method using low-priced type MCU.

• The Journal of Korean Institute of Electromagnetic Engineering and Science
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• v.14 no.8
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• pp.863-870
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• 2003

The digital transmission system entered in a RF region as digital system use IC chips of the speeder edge rate and clock speed nowadays. Optical path really was used in order to obtain the more capacity. In this paper, we described importance of electrical interconnect to get the signal integrity in optical module by simulation and experiment. 12 channel${\times}$2.5 G/ps optical parallel transmitter modules were manufactured by two different method ; access lines with microstrip and stripline type. We have clearly shown that the optical module adopting microstrip type with S$\sub$11/ $\geq$ -10 dB presents distortion but the optical module adopting stripline type with S$\sub$11/ $\leq$ : 15 dB obtains eye opening in 2.5 Gbis optical eye pattern response.

• The Journal of Korean Institute of Electromagnetic Engineering and Science
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• v.18 no.3 s.118
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• pp.298-304
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• 2007

In this paper, the antenna which has a multiband operation (GSM850, EGSM, DCS1800, USPCS, W-CDMA) is proposed. This antenna was designed by the commercial software HFSS 3-D EM simulator, and it is organized by using a meander branch structure which has a via and lines on FR-4$(\varepsilon_r=4.4)$ substrate. Especially, it has a gap feeding structure which makes good operation at overall bandwidth. The designed antenna is manufactured by PCB processing, and measured by using a network analyzer and a test chamber. The manufactured antenna with the dimension of 8 mm width, 20 mm height and 3.2 mm thickness is able to applied as an internal antenna for multiband mobile phones.

• Journal of the Korean Society for Aeronautical & Space Sciences
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• v.33 no.9
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• pp.104-112
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• 2005

This paper presents the technique to develop an operational flight program(OFP) of avionic system computer(ASC) which integrates the avionics control, navigation and fire control and provides informations for flight, navigation and weapon aiming missions. For the development of the OFP of ASC, two i960KB chips are used as central processing units board and standard computer interface library(SCIL) which is built in house is used. The Irvine compiler corporation(ICC) integrated development environment(IDE) and the programming language Ada95 are used for the OFP development. We designed the OFP to a computer software configuration item(CSCI) which consists of to three parts for independency of software modules. The OFP has been verified through a series of flight tests. The relevant tests also have been rigorously conducted on the OFP such as software integrated test, and ground functional test.

• Journal of the Korea Society of Computer and Information
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• v.15 no.2
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• pp.9-18
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• 2010

High performance is required with small size and low power in the mobile embedded system. A CORDIC algorithm can compute transcendental functions effectively with only small adders and shifters and is suitable one for the mobile embedded system. However CORDIC unit has performance degradation according due to iterative inter-rotations. Adder design is an important design unit to be optimized for a high performance and low power CORDIC unit. It is necessary to explore the design space of a CORDIC unit considering trade-offs of an adder unit while satisfying delay, area and power constraints. In this paper, we suggest a CORDIC architecture employing a heterogeneous adder and an optimization methodology for producing better optimal tradeoff points of CORDIC designs.

• Journal of Digital Contents Society
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• v.11 no.1
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• pp.99-104
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• 2010

Numerous bio-digital contents have been produced by new technology using biochip and others for analyzing early chemical-induced genes. These contents have little meaning by themselves, and so they should be modified and extracted after consideration of biological meaning. These include genomics, transcriptomics, protenomics, metabolomics, which combined into omics. Omics tools could be applied into toxicology, forming a new field of toxicogenomics. It is possible that approach of toxicogenomics can estimate toxicity more quickly and accurately by analyzing gene/protein/metabolite profiles. These approaches should help not only to discover highly sensitive and predictive biomarkers but also to understand molecular mechanism(s) of toxicity, based on the development of analysing technology. Furthermore, it is important that bio-digital contents should be obtained from specific cells having biological events more than from whole cells. Taken together, many bio-digital contents should be analyzed by careful calculating algorism under well-designed experimental protocols, network analysis using computational algorism and related profound databases.

• Proceedings of the Korean Institute of Information and Commucation Sciences Conference
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• 2013.10a
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• pp.809-812
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• 2013

This paper realize power control embedded system with one master of Core-A 32-bit RISC processor and several slaves controling power with synchronized digital signals. Core-A platform provided by Dynalith Systems consists of Core-A processor, AMBA bus, SSRAM, AC97, DMA, UART, GPIO etc. Slave is made by both digital part and analog part. The former generates various power control patterns synchronized with master signal. The latter converts 220V power proportional to 4 bit digital signals. Design of Embedded system is executed in Flowrian2 of System Centroid Inc., in which software is cross-compiled and hardware is verified by simulation. Embedded system is implemented in FPGA board and CPLD chips as well as PCB board for analog power control.

• The Journal of Korean Institute of Communications and Information Sciences
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• v.38B no.6
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• pp.427-434
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• 2013

In this paper, the design and layout of a 2.5 Gbps arrayed VCSEL driver for optical transceiver having arrayed multi-channel of integrating module is confirmed. In this paper, a 4 channel 2.5 Gbps VCSEL (vertical cavity surface emitting laser) driver array with automatic optical power control is implemented using $0.18{\mu}m$ CMOS process technology that drives a $1550{\mu}m$ high speed VCSEL used in optical transceiver. To enhance the bandwidth of the optical transmitter, active feedback amplifier with negative capacitance compensation is exploited. We report a distinct improvement in bandwidth, voltage gain and operation stability at 2.5Gbps data rate in comparison with existing topology. The 4-CH chip consumes only 140 mW of DC power at a single 1.8V supply under the maximum modulation and bias currents, and occupies the die area of $850{\mu}m{\times}1,690{\mu}m$ excluding bonding pads.

• Journal of the Institute of Electronics Engineers of Korea SD
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• v.40 no.5
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• pp.335-344
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• 2003

The image compression based on discrete wavelet transform has been widely accepted in industry since it shows no block artifacts and provides a better image quality when compressed to low bits per pixel, compared to the traditional JPEG. The coefficients generated by discrete wavelet transform are quantized to reduce the number of code bits to represent them. After quantization, lossless coding processes are usually applied to make further reduction. This paper presents a new and efficient lossless coding algorithm for quantified wavelet coefficients based on the statistical properties of the coefficients. Combined with discrete wavelet transform and quantization processes, our algorithm has been implemented as an image compression chip, using 0.5${\mu}{\textrm}{m}$ standard cells. The experimental results show the efficiency and performance of the resulting chip.