• Proceedings of the Materials Research Society of Korea Conference
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• 2003.03a
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• pp.65-65
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• 2003

청색 발광 LEDs의 개발과 상용화 이후에 백색조명등의 응용 가능성으로 인하여 이에 대한 많은 연구가 최근에 계속되고 있다 하지만 GaN의 많은 광학적인 장점에도 불구하고 이러한 소자의 기판으로 사용되고 있는 sapphire의 열악한 열적 특성은 소자의 열화를 야기할 수 있으며 특히 고출력작동 시에 소자성능 저하의 원인이 될 수 있다. 따라서 이러한 GaN를 기본으로 하는 LED의 경우 이에 대한 정확한 열 측정과 고출력 작동 시의 열적 모델링은 칩과 패키징 단위에서 모두 중요한 연구분야가 되고 있다. 고출력 GaN LED에 대하여 신뢰성에 관한 몇 가지 보고가 있지만, 이러한 보고의 대부분은 패키징 된 램프에 대한 분석이며 정작 칩에 대한 근본적인 열 분석과 신뢰성에 대한 연구결과는 미미한 실정이다 따라서 본 연구에서는 GaN LED 칩에 대하여 직접적인 열 분석을 시도하였다

• Transactions of the Korean Society of Mechanical Engineers A
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• v.25 no.6
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• pp.959-964
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• 2001

An experimental investigation on the near-field electromagnetic loss of thin copper layers has been presented using microfabricated microwave transceivers for applications to multi-chip microsystems. Copper layers in the thickness range of 0.2$\mu$m∼200$\mu$m have been electroplated on the Pyrex glass substrates. Microwave transceivers have been fabricated using the 3.5mm$\times$3.5mm nickel microloop antennas, electroformed on the silicon substrates. Electromagnetic radiation loss of the copper layers placed between the microloop transceivers has been measured as 10dB∼40dB for the wave frequency range of 100MHz∼1GHz. The 0.2$\mu$m-thick copper layer provides a shield loss of 20dB at the frequencies higher than 300MHz, whereas showing a predominant decreases of shield loss to 10dB at lower frequencies. No substantial increase of the shield effectiveness has been found for the copper shield layers thicker that 2 $\mu$m.

• Transactions of the Korean Society of Mechanical Engineers A
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• v.28 no.4
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• pp.435-442
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• 2004

This paper presents a hermetic MEMS on-chip package bonded by a closed-loop AuSn solder-line. We design three different package specimens, including a substrate heated specimen without interconnection-line (SHX), a substrate heated specimen with interconnection-line (SHI) and a locally heated specimen with interconnection-line (LHI). Pressurized helium leak test has been carried out for hermetic seal evaluation in addition to the critical pressure test for bonding strength measurement. Substrate heating method (SHX, SHI) requires the bonding time of 40min. at 400min, while local heating method (LHI) requires 4 min. at the heating power of 6.76W. In the hermetic seal test. SHX, SHI and LHI show the leak rates of 5.4$\pm$6.7${\times}$$^{-10}$ mbar-l/s, 13.5$\pm$9.8${\times}$$^{-10}$ mbar-l/s and 18.5$\pm$9.9${\times}$$^{-10}$ mbar-l/s, respectively, for an identical package chamber volume of 6.89$\pm$0.2${\times}$$^{-10}$. In the critical pressure test, no fracture is found in the bonded specimens up to the applied pressure of 1$\pm$0.1MPa, resulting in the minimum bonding strength of 3.53$\pm$0.07MPa. We find that the present on-chip packaging using a closed AuSn solder-line shows strong potential for hermetic MEMS packaging with interconnection-line due to the hermetic seal performance and the shorter bonding time for mass production.

• Journal of the Microelectronics and Packaging Society
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• v.23 no.3
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• pp.1-6
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• 2016

The Internet of Things (IoT) is a new technology paradigm demanding one packaged system of various semiconductor and MEMS devices. Therefore, the development of electronic packaging technology with very high connectivity is essential for successful IoT applications. This paper discusses both fan-out wafer level packaging (FOWLP) and 3D stacking technologies to achieve the integrattion of heterogeneous devices for IoT. FOWLP has great advantages of high I/O density, high integration, and design flexibility, but ultra-fine pitch redistribution layer (RDL) and molding processes still remain as main challenges to resolve. 3D stacking is an emerging technology solving conventional packaging limits such as size, performance, cost, and scalability. Among various 3D stacking sequences wafer level via after bonding method will provide the highest connectivity with low cost. In addition substrates with ultra-thin thickness, ultra-fine pitch line/space, and low cost are required to improve system performance. The key substrate technologies are embedded trace, passive, and active substrates or ultra-thin coreless substrates.