• Proceedings of the Korean Institute of Electrical and Electronic Material Engineers Conference
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• 2004.07b
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• pp.1214-1217
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• 2004

현재 전기용량의 국가표준은 1 kHz, 1592 Hz에서만 유지 및 보급이 되고 있다. 그러나 전기용량 및 임피던스를 측정하는 브리지와 LCR meter들은 비교적 넓은 주파수 범위에서 측정이 가능하도록 생산이 되고 있다. 따라서 이러한 기기들의 교정은 실제적으로 사용되고 있는 주파수 전 영역이 아닌 1 kHz 만 되고 있어서 완전한 교정이라고 할 수 없다. 본 논문에서는 이를 해결하기위하여 임피던스 analyzer의 one-port 측정기술을 사용하여 4-terminal-pair(이하 4TP) 전기용량 표준기 각각의 terminal에서 임피던스를 필요 주파수에서 측정하고, 측정된 임피던스 matrix를 이용하여 4TP의 transfer 어드미턴스와 출력임피던스를 계산 하였다.

• Journal of Korea Society of Industrial Information Systems
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• v.18 no.5
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• pp.25-32
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• 2013

A 1.8V 2-Gb/s scalable low voltage signaling (SLVS) transmitter (TX) is designed for mobile applications requiring high speed and low power consumption. It consists of 4-lane TX for data transmission, 1-lane TX for a source synchronous clocking, and a 8-phase clock generator. The proposed SLVS TX has the scaling voltage swing from 50 mV to 650 mV and supports a high speed (HS) mode and a low power (LP) mode. An output impedance calibration scheme for the SVLS TX is proposed to improve the signal integrity. The proposed SLVS TX is implemented by using a 0.18-${\mu}m$ 1-poly 6-metal CMOS with a 1.8 V supply. The simulated data jitter of the implemented SLVS TX is about 8.04 ps at the data rate of 2-Gb/s. The area and power consumption of the 1-lane of the proposed SLVS TX are $422{\times}474{\mu}m^2$ and 5.35 mW/Gb/s, respectively.

• Proceedings of the Korean Institute of Information and Commucation Sciences Conference
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• 2013.10a
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• pp.357-360
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• 2013

A 1.8V 2-Gb/s scalable low voltage signaling (SLVS) transmitter (TX) is designed for mobile applications requiring high speed and low power consumption. It consists of 4-lane TX for data transmission, 1-lane TX for a source synchronous clocking, and a 8-phase clock generator. The proposed SLVS TX has the scaling voltage swing from 50 mV to 650 mV and supports a high speed (HS) mode and a low power (LP) mode. An output impedance calibration scheme for the SVLS TX is proposed to improve the signal integrity. The proposed SLVS TX is implemented by using a $0.18-{\mu}m$ 1-poly 6-metal CMOS with a 1.8V supply. The simulated data jitter of the implemented SLVS TX is about 8.04 ps at the data rate of 2-Gbps. The area and power consumption of the 1-lane of the proposed SLVS TX are $422{\times}474{\mu}m^2$ and 5.35 mW/Gb/s, respectively.