• Journal of the Institute of Electronics Engineers of Korea SC
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• v.44 no.1
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• pp.1-11
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• 2007

In this paper, a new fully digital control method for UPS inverter, which is based on the double control loop such as the outer voltage control loop and inner current control loop, is proposed. In the proposed control system, overshoots and oscillations due to the computation time-delay are compensated by explicit incorporation of the time-delay in the current control loop transfer function. The inner current control loop is adopted by an internal model controller. The internal model controller is designed to a second order deadbeat reference-to-output response which means that its response reaches the reference in two sampling time including computational time-delays. The outer voltage control loop employing P-Resonance controller is proposed. The resonance controller has an infinite gain at resonant frequency, and the resonant frequency is set to the fundamental frequency of the reference voltage in this paper. Thus the outer voltage control loop causes no steady state error as regard to both magnitude and phase. The effectiveness of the proposed control system has been verified by the simulation and experimental results respectively.

• Journal of Korea Multimedia Society
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• v.11 no.9
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• pp.1310-1323
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• 2008

Recently, many studies on automated generation of composite Web services have been done. Most of these works compose Web services by chaining their inputs and outputs, but do not consider the functional semantics. Therefore, they may construct unsatisfied composite services against users' intention. Futhermore, they have high time-complexity since every possible combinations of available services should be considered. To resolve these problems, this paper proposes a sophisticated composition method that explicitly specifies and uses the functional semantics of Web services. Specifically, A graph model is constructed to represent the functional semantics of Web services as well as the dependency among inputs and outputs. On the graph, we search core services which provide the requested function ality and additional services which transform between I/O types of the user request and the core services. Then, composite services are built from combinations of the discovered services. The proposed method improves the semantic correctness of composite services by the functional semantics of Web services, and reduces the time complexity by combinations of functionally related services.

• Journal of the Institute of Electronics Engineers of Korea SD
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• v.38 no.1
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• pp.55-68
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• 2001

This paper presents a new ALU architecture to minimize glitching power consumption which is appeared in the conventional one with P(carry propagation)/G(carry generation) blocks. In general, A lot of glitches generated once are propagating into the next stage of circuits to make unnecessary power dissipation. Therefore, a new ALU architecture which removes the glitches at the output of P/G blocks is presented in this paper. If a lot of glitches at the output of P/G blocks are removed, then the signal transitions caused by glitches are reduced in the sum generation block and hence power consumption is also reduced. A latch is inserted into the conventional P/G blocks to remove the glitches at the output of P/G blocks. Latch enable signal can make a role in eliminating a lot of glitches at the P/G's outputs by controlling output enable time. Experimental results from HSPICE simulations with implementing 16-b ALU show 28% reduction in glitching power consumption with negligible delay penalty.

• Journal of the Institute of Electronics Engineers of Korea SD
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• v.41 no.8
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• pp.75-84
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• 2004

In this paper, we proposed an efficient hardware architecture of line-based lifting algorithm for Motion JPEG2000. We proposed a new architecture of a lifting-based filtering cell which has an optimized and simplified structure. It was implemented in a hardware accommodating both (9,7) and (5,4) filter. Since the output rate is linearly proportional to the input rate, one can obtain the high throughput through parallel operation simply by adding the hardware units. It was implemented into both of ASIC and FPGA The 0.35${\mu}{\textrm}{m}$ CMOS library from Samsung was used for ASIC and Altera was the target for FRGA. In ASIC, the proposed architecture used 41,592 gates for the lifting arithmetic and 128 Kbit memory. For FPGA it used 6,520 LEs(Logic Elements) and 128 ESBs(Embedded System Blocks). The implementations were stably operated in the clock frequency of 128MHz and 52MHz, respectively.

• Journal of the Institute of Electronics Engineers of Korea TC
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• v.37 no.7
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• pp.1-8
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• 2000

In this paper, we introduce a modified interference cancellation scheme for multiuser detection in CDMA(Code Division Multiple Access). This detector uses SIC(Successive Interference Canceller) scheme and divides the received signals to reduce the delay time. In this proposed structure, the active users are divided into a number of groups. Within each group, parallel detection is performed to estimate the output signal of that group. The estimated output signal due to that group is then subtracted from the received signal and the resulting residual signal is used for the parallel detection of the next group. This parallel and serial cancellation process is repeated until the last group in the stage is completed. The estimated output signals due to all groups except -th group are MAI for the user signals in -th group. Therefore, the estimated output signals due to all groups except th group are subtracted from the received signal, and then the obtained signal becomes the input signal of -th SIC. The proposed RDSIC (Reduced Delay time of Successive Interference Canceller) has performance and complexity close to the SIC, but with much less detection delay.

• Journal of KIISE:Information Networking
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• v.30 no.4
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• pp.520-534
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• 2003

In this paper, a performance evaluation model of the Fat-tree Network with the multiple-buffered crossbar switches is proposed and examined. Buffered switch technique is well known to solve the data collision problem of the switch network. The proposed evaluation model is developed by investigating the transfer patterns of data packets in a switch with output-buffers. Two important parameters of the network performance, throughput and delay, are then evaluated. The proposed model takes simple and primitive switch networks, i.e., no flow control and drop packet, to demonstrate analysis procedures clearly. It, however, can not only be applied to any other complicate modern switch networks that have intelligent flow control but also estimate the performance of any size networks with multiple-buffered switches. To validate the proposed analysis model, the simulation is carried out on the various sizes of Fat-tree networks that uses the multiple buffered crossbar switches. Less than 2% differences between analysis and simulation results are observed.

• Proceedings of the Korean Vacuum Society Conference
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• 2010.08a
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• pp.102-102
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• 2010

수 Tera Watt급의 가속기 및 펄스파워 시스템은 다수의 스위치를 사용하고 있으며, 이와 같은 가속기 및 시스템의 성능은 기체방전 스위치의 성능에 직접적으로 관련되어 있다. 일반적으로 이와 같은 기체방전, 액체방전 고출력 스위치는 다목적으로 많은 연구와 개발에 응용되고 있다. 예를 들어 천둥 펄스전자빔 발생장치는 12개의 Marx gap 및 3개의 100 kV 펄스충전 전기트리거 gap을 가지고 있다. 기체 방전 또는 액체 방전 펄스 충전 갭 스위치의 음극에 펄스 고전압이 인가되면 이로 인하여 음극에서 전자빔이 발생한다. 내부에는 전자빔이 양극과 충돌하는 순간 양극표면에 플라스마가 형성된다. 이와 같은 플라스마 sheath는 축 방향 이극관 안에서 양극충전 에서 음극으로 팽창하면서 전파하며, 또한 거의 동시에 음극표면에도 플라스마가 형성되어 음극에서 양극으로도 팽창하여 전파하게 된다. 이와 같은 펄스충전 고출력 갭 스위치 안에서 발생되는 방전 플라스마의 특성에 관한 갭 breakdown 과정에 대한 특성연구를 한다. 고출력스위치의 특성 조건으로는 방전전압, 방전시간, jitter 등이 있다. 본 연구에서는 최대전압 600 KV, 최대전류 88 KA, 펄스 폭 60 ns의 특성을 가지는 고전압펄스 시스템 '천둥'을 이용하여 방전 챔버에 고전압 펄스를 인가하고 N2와 SF6 혼합기체 종류와 압력에 따른 방전 현상을 연구하였다. 전극은 구리텅스텐 합금재질의 표준전극을 사용하였고, 전극 간격은 20 mm로 고정하였다. 방전 챔버 압력을 100 torr에서 4 기압까지 변화시켜가며 실험을 진행하였고, N2에 대한 SF6의 혼합비율을 0%~100%까지 변화시키며 실험을 진행하였다. 방전 챔버에는 C-dot probe와 B-dot probe를 설치하여 전압과 전류를 측정하였고, C-dot probe 와 B-dot probe는 각각 Northstar사의 10000:1 고전압 probe와 rogowiski coil을 이용하여 시준 하였다. 실험결과 방전전압은 압력이 증가함에 따라 증가하다가 2 기압 이상에서는 완만히 증가하는 경향을 보였고, SF6 혼합비율은 0~10%까지 급격히 증가하고, 그 이상의 혼합비율에서는 완만히 증가하였다. 방전개시시간은 혼합기체 압력에 따라 증가하며 1기압 이상에서는 급격히 증가 하였다. SF6 혼합비율에 따라서는 1 기압 조건까지는 큰 차이가 없었으나 2 기압부터는 급격히 증가하였다. 안정성을 나타내는 jitter는 SF6 100%일 때 가장 컸으나 혼합기체의 변화에 따른 큰 차이는 없었다.

• Progress in Medical Physics
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• v.11 no.2
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• pp.141-146
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• 2000

Power spectrum analysis is a powerful noninvasive tool for quantifying autonomic nervous system activity. In this paper, We developed a measuring system for Autonomic Nervous Activity by using power spectrum analysis method to obtain the activities of autonomic nervous system. This system adopt a isolated power for patient's safety. In this system, Two output signal is obtained - R-R interval time variability and Respiration time variability. Time variability is use to find out some disease related to Autonomic Nervous System. Experimental tested range is 30 ～ 240 BPM for ECG and 15～80 BPM for Respiration.

• The Optical Journal
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• s.144
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• pp.16-24
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• 2013

펨토초는 1000조 분의 1초를 말한다. $10^{-15}$를 의미하는 단위명이 펨토(Femto)이기 때문에 붙여진 이름이다. 눈을 한 번 깜박이는 시간이 약 10분의 1초, 총알이 물체를 통과하는 데 걸리는 시간이 약 100만 분의 5초인 점을 감안하면 펨토초는 상상하기도 힘들 정도로 빠른 시간인 셈이다. 이런 펨토초 동안 벌어지는 물리, 화학, 생물학적 현상을 연구하는 학문이 펨토과학이며 주로 펨토초 레이저를 이용해 관찰한다. 현재 전 세계적으로 펨토초의 극히 짧은 시간에 1000조 와트(페타와트)의 고출력 레이저를 발생시킬 수 있는 광양자빔 연구시설 구축 사업이 활발하게 진행되고 있다. 국내에서는 광주과학기술원(GIST) 고등광기술연구소가 '극초단 광양자빔 연구시설 설치 운영사업(사업책임자: 이종민 교수)'을 통해 국가 대형 레이저 연구시설인 '페타와트 극초단 초강력 레이저 연구시설(PULSER)'을 최근 구축 완료했다. 이번호에서는 21세기를 이끌 신성장동력 중 하나로 각광 받고 있는 펨토과학기술의 국내 연구 현황과 페타와트 극초단 초강력 레이저 연구시설(PULSER)에 대해 자세히 소개하고자 한다.

• Proceedings of the Korean Information Science Society Conference
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• 2006.06a
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• pp.175-177
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• 2006

휴대폰에 임베디드 리눅스를 탑재하고자 할 경우 전력소모, 경량화, 빠른 부팅, 실시간, 보안 등과 관련한 추가고려사항이 발생한다. 본 연구에서는 휴대폰용 임베디드 리눅스의 커널 부팅시간을 단축시키기 위한 구체적인 방법을 제시하고 실제적인 적용을 통하여 그 성능을 평가한다. 측정된 데이터를 바탕으로 커널내부에서 가장 많은 시간을 소요하는 함수들을 찾아내고 확인된 함수들에 대해서 초기화 지연회피, 불필요한 장치 드라이버 제거, 불필요한 커널 메시지 미출력 등의 기법들을 각각 적용한다. 제안된 기법을 모두 적용할 경우에 기존 커널 부팅시간을 50%정도 단축시킬 수 있었다.