• Journal of the Korean Society for Precision Engineering
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• v.19 no.10
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• pp.60-65
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• 2002

For optimal design of micro stage, we measured the displacement of piezoelectric transducer that was based on voltage value. And the micro stage was analyzed using FEM with displacement data including voltage value of piezoelectric transducer. For verification of analysis results, the displacements were measured by using Laser-interferometer. And researchers confirmed to propriety on design of micro stage with FEM, we obtained 3.5% error rate between measurement results and analyzing results.

• Journal of the Institute of Electronics Engineers of Korea SD
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• v.43 no.6 s.348
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• pp.47-52
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• 2006

This paper proposes a novel low-power $32bit\times32bit$ multiplier for deep submicron technologies beyond 130nm. As technology becomes small, static power due to leakage current significantly increases, and it becomes comparable to dynamic power. Recently, shutdown method based on MTCMOS is widely used to reduce both dynamic and static power. However, it suffers from severe power line noise when restoring whole large-size functional block. Therefore, the proposed multiplier mitigates this noise by shutting down and waking up sequentially along with pipeline stage. Fabricated chip measurement results in $0.35{\mu}m$ technology and gate-transition-level simulation results in 130nm and 90nm technologies show that it consumes $66{\mu}W,\;13{\mu}W,\;and\;6{\mu}W$ in idle mode, respectively, and it reduces power consumption to $0.04%\sim0.08%$ of active mode. As technology becomes small, power reduction efficiency degrades in the conventional clock gating scheme, but the proposed multiplier does not.