Analysis of Drain Induced Barrier Lowering of Asymmetric Double Gate MOSFET for Channel Doping Concentration (비대칭 DGMOSFET의 채널도핑농도에 따른 드레인 유도 장벽 감소현상 분석)
-
- Proceedings of the Korean Institute of Information and Commucation Sciences Conference
- /
- 2015.10a
- /
- pp.858-860
- /
- 2015