• Proceedings of the KIEE Conference
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• 2011.07a
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• pp.762-763
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• 2011

19세기말에 차동보호계전방식이 이미 적용되었고 시스템 보호에 가장 먼저 사용되는 방식 중에 하나였다. 이 방식은 고장전력설비의 기기를 보호하기위해 전류의 입출력값을 비교함으로 고장을 검출하는 방법을 사용한다. 결과적으로 비율차동보호방식은 완벽하게 고장구간을 검출할 수 있으므로 전력설비의 중요기기의 주보호로 적합한 시스템이라고 볼 수 있다. 본 논문 변압기의 내/외부사고유형에 따른 전자기계식과 디지털 보호계전기의 동작특성을 컴퓨터기반의 해석 S/W를 이용하여 모델링과 동작특성에 대한 분석을 통해 보호계전기 동작특성의 신뢰성검증과 전력계통을 시뮬레이션하기 위해 구성하였다. 특히, 비율차동특성 보호 알고리즘을 계전기별로 모듈화하기 위한 기본 구조설계에 초점을 맞추었고 외부사고에 대해 각 보호계전기 동작특성을 비교함으로써 보호계전기 응답특성에 검증하는 기초 데이터를 생성하는 과정도 기술하였다.

• The Journal of Korean Institute of Electromagnetic Engineering and Science
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• v.16 no.5 s.96
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• pp.494-500
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• 2005

In this paper, optical noise is reduced by a differential detector with an optical fiber coupler in an optical wireless system. An $1\times2$ optical fiber coupler divides the received optical signal by 2 equally, and connects them to the two photodiodes in a differential detector. The output voltage variation due to the abrupt change of optical noise distribution in space disappears because the two photodiodes effectively detect the optical signal at the same point. The signal to noise ratio in a differential detector with a fiber coupler was 8 dB higher than in a single photodiode with an optical filter.

• Korean Journal of Optics and Photonics
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• v.15 no.3
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• pp.229-233
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• 2004

We propose a novel scheme to suppress the multiple-access interference(MAI) in coherent optical CDMA systems. This is based on a differential detection using the dual-control NOLM. For an experimental demonstration, two encoded channels we constructed and decoded. These decoded signals are sent to the dual-control NOLM and a high autocorrelation peak with suppressed MAI at the output of the NOLM is observed. Signal-to-interference ratio is improved by 7 ㏈.

• Journal of the Institute of Electronics Engineers of Korea TC
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• v.43 no.10 s.352
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• pp.60-68
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• 2006

OFDM(Orthogonal Frequency Division Multiplexing) is widely used in wideband wireless communication systems due to its excellentperformance. One of the most important operations in the OFDM receivers is preamble detection. This paper presents a differential detection method with moving average filter, which is similar to extended differential detection, and a filter determination method to achieve the best performance invarious environments. The proposed method show that the optimal filter size decreases as the delay spread increases and as the signal-to-noise ratio increases.

• Proceedings of the Korean Institute of Communication Sciences Conference
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• 1992.06a
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• pp.704-707
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• 1992

• Journal of Korea Society of Industrial Information Systems
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• v.19 no.3
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• pp.1-7
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• 2014

This paper describes the implementation of high speed comparator for the ATE (automatic test equipment) system. The comparator block is composed of continuous comparator, differential difference amplifier(DDA) and output stage. For the wide input dynamic range of 0V to 5V, and for the high speed operation (1~800MHz), high speed rail-to-rail amplifier is used in the first stage. And hysteresis circuits, pre-amp and latch are followed for high speed operation. To measure the difference of output signals between the two devices under test (DUTs), a DDA is applied because it can detect the differences of both common signals and differential signals. This comparator chip was implemented with $0.18{\mu}m$ BCDMOS process and can compare the signal difference of 5mV up to the frequency range of 800 MHz. The chip area of the comparator is $620{\mu}m{\times}830{\mu}m$.

• The Journal of Korean Institute of Electromagnetic Engineering and Science
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• v.11 no.3
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• pp.365-371
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• 2000

In this paper, we introduce a noise reduction method using polarizers in a wireless optical interconnections. If we use polarizers in a differential detector, the noise reduction capability is improved. In a case that two optical signal beams of similar wavelength are overlapped in space and crosstalk is a serious problems, we can detect each channel separately without crosstalk using two orthogonal polarizers. This method is very simple and easy to use.

• Journal of the Korea Institute of Information and Communication Engineering
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• v.16 no.2
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• pp.313-318
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• 2012

This paper presents an automatic system to detect variety of faults from fine pitch COF(chip-on-film) which is less than $30{\mu}m$. Developed system contains circuits and technique to detect fast various faults such as hard open, hard short, soft open and soft short from fine pattern. Basic principle for fault detection is to monitor fine differential voltage from pattern resistance differences between fault-free and faulty cases. The technique uses also radio frequency resonator arrays for easy detection to amplify fine differential voltage. We anticipate that proposed system is to be an alternative for conventional COF test systems since it can fast and accurately detect variety of faults from fine pattern COF test process.

• Proceedings of the KIEE Conference
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• 2001.07d
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• pp.2299-2301
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• 2001

광 디스크의 용량을 증가시기키 위해선, 레이저 다이오드의 단파장화와 렌즈의 개구수 증가가 수년 동안 시도되어왔다. 불행히도 이러한 노력들은 디스크 틸트(tilt)로 인해 야기되는 코마(coma) 수차로 인한 부작용을 유발하였다. 이런 문제를 해결하기 위해, 램(random access memory, RAM) 디스크의 경우 몇 가지 검출과 보상 방법이 제안되었다. 그러나, 롬(read only memory, ROM) 디스크의 경우 아직까지 뚜렷한 해결책이 제시되지 않고 있다. 본 논문에서는 8분할 광 검출기에 의해 생성되는 차동 위상 검출(differential phase detection, DPD) 신호를 이용한 고밀도 롬 디스크에서 래디얼(radial) 틸트를 검출하는 방법을 제안한다. 3축 렌즈 구동형 액츄에이터(actuator)를 이용하여 개발한 래디얼 틸트 서보로 검출된 래디얼 틸트를 보상한다. 액츄에이터의 회전이 트래킹(tracking) 서보(servo)에 미치는 영향을 소개한다. 끝으로 제안된 방법의 유용성을 고밀도 롬 드라이브에 대한 실험을 통해 검증한다.

• Journal of the Institute of Electronics Engineers of Korea SD
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• v.43 no.10 s.352
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• pp.28-33
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• 2006

An integrated 3.125Gbps clock and data recovery (CDR) circuit is presented. The circuit does not need a reference clock. It has a phase and frequency detector (PFD), which incorporates a bang-bang type 4X oversampling PD and a rotational frequency detector (FD). It also has a ring oscillator type VCO with four delay stages and three zero-offset charge pumps. With a proposed PD and m, the tracking range of 24% can be achieved. Experimental results show that the circuit is capable of recovering clock and data at rates of 3.125Gbps with 0.18 um CMOS technology. The measured recovered clock jitter (p-p) is about 14ps. The CDR has 1.8volt single power supply. The power dissipation is about 140mW.