• Electronics and Telecommunications Trends
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• v.9 no.4
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• pp.23-34
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• 1994

직렬 접속 프로토콜은 두개 이상의 근거리 시스템간의 정보 교환에 사용된다. 현재까지 공식적인 기관에서 표준화되어 제정된 직렬 접속 규격들이 가지고 있는 성능은 전송 속도 측면에서 수 kbps에서 최대 10Mbps급에 한정되어 있는 관계로 수백 Mbps 혹은 수 Gbps급에 달하는 직렬 접속 프로토콜 성능을 요구하는 고성능 통신 및 정보 처리 시스템을 위한 새로운 직렬 접속 규격이 요구되고 있다. IEEE에서 표준화 작업중인 Multi-CPU 병렬 시스템을 위한 접속 규격인 P1355 접속 규격은 경제적이며 용이한 확장성을 가지는 칩과 칩간외에 보드와 보드간 혹은 랙과 랙간의 연결이 가능한 표준 규격안이다. P1355 접속 프로토콜은 특성이 서로 다른 DS, TS, HS link 규격들로 구성되어 있으며 이들은 선로 동작 속도 측면에서 각각 200Mbps, 250Mbps, 1Gbps의 성능을 가지고 있으며, 사용되는 데이터 심볼의 코딩 방식, 접속로 동작 초기화 및 오류 제어, 접속로의 물리적 성능 및 규격 등에서 차이를 가지고 있다. P1355는 일반적인 통신용 전송 선로에서 요구되는 물리 계층의 BER 성능보다 $10^5$에서 $10^10$배 향상된 선로 BER 특성과 이러한 하위 계층 특성을 바탕으로한 패킷 손실이 없는 간결한 상위계층 프로토콜을 특징으로 하며, 차세대 통신 수단인 ATM교환기 시스템의 서브 시스템 접속 규격으로 사용될 수 있다.

• Proceedings of the KIPE Conference
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• 2017.07a
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• pp.54-55
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• 2017

배전계통에서 병렬아크는 전선이나 노후된 설비의 절연파괴에 따른 합선에 의하여 발생하고 직렬아크는 차단기, 소켓-플러그, 커플러 등 접속기에서 부하와 전원이 분리되는 경우에 발생한다. 이러한 아크현상에 대응하기 위해서는 아크의 특성을 해석하고 그에 따른 아크소호방법이 제시되어야 한다. 병렬아크는 1889년 발견된 Paschen의 법칙에 따르며, 평행한 금속판 사이에 아크방전이 시작되는 항복전압이 매질가스의 종류 및 압력과 개리거리에 따른 함수로 규정된다. 반면, 직렬아크는 아직까지 명확한 해석방법이 제시되어있지 못하다. 본 논문에서는 직류 차단기에서 발생하는 직렬 차단 아크의 촉발과 지속적인 발생, 소호에 대한 특성을 분석하여 3가지 특성을 기반으로 하는 직렬 차단아크전류 모델을 제안하고 실험을 통하여 검증하였다.

• The Journal of Korean Institute of Communications and Information Sciences
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• v.28 no.1A
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• pp.47-53
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• 2003

This paper describes the design of a 155 Mb/s multiplexer-demultiplexer chip. This device for a 2.5 Gb/s SDH based transmission system is to interleave the parallel data of 51 Mb/s into 155 Mb/s serial data output, and is to deinterleave a serial input bit stream of 155 Mb/s into the parallel output of 51 Mb/s The input and output of the device are TTL compatible at the low-speed end, but 100K ECL compatible at the high-speed end The device has been fabricated with a 0.7${\mu}m$ BiCMOS gate array The fabricated chip shows the typical phase margin of 180 degrees and output data skew less than 470 ps at the high-speed end. And power dissipation is evaluated under 2.0W.

• The Journal of Korean Institute of Communications and Information Sciences
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• v.13 no.2
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• pp.160-170
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• 1988

This paper describes the outboard NIU(Network Interface Unit) using microprocessor and the hardware and software of concentrator for constructing star typed LAN(Local Area Network) based on token ring method. The NIU adapter can adapter up to four parallel and serial typed terminals. Because it has PAD function on input output data, any type of terminals can be adapted. Since the concentrator has logical switching circuit which enables data to bypass the faulted NIU adapter, this network prevents communication break. When user transmits and receives data, the concentrator constructs star typed LAN which connct both transmitting and receiving sides. A s result, this network eliminated ring latency time in other NIU exculding transmitting and receiving NIU. So the throughput of this LAN is increased. Because this LAN system consists of several modultes according to it's function, the expansion of function or the modification of method is easy.

• Journal of the Korean Institute of Illuminating and Electrical Installation Engineers
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• v.20 no.8
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• pp.22-29
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• 2006

According to the recent revision of KS on the basis of the IEC, equipotential grounding systems has been come into focus and the use of surge protective devices(SPD) has been increased radically in order to operate the power system stably. $Z_nO$ varistor with non-linear resistance, which has an outstanding voltage-current(V-I) characteristic, is mainly used in power system to limit surge voltage and divert surge current. $Z_nO$ varistors are packaged several types based on the circuit assembly to be connected to a.c. power line. When the user assemble the $Z_nO$ varistors into parallel or series circuit package, there are my things to be taken into consideration including functions and thermal stability because they are directly related to the safety. We compare stabilities of each assembly type by measuring residual voltage, discharge current, leakage current and surface temperature concerned to the protection performances between a single device with a 40[kA] of current capacity and parallel or series circuits type of varistor package.

• The Journal of Korean Institute of Communications and Information Sciences
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• v.22 no.12
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• pp.2653-2663
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• 1997

The successive and parallel interference cancellation schemes are two well-known types of multi-stage interference cancellation schemes using the conventional correlator receivers as a basic building block, which has been known to significantly improve the performance of DS/CDMA system in the multiple access communication. Performance comparison between these two schemes is made strictly based on the analytical and it has been shown that the successive interference cancellation (SIC) scheme is more resistant to fading than the parallel interference cancellation (PIC) scheme. We further investigate the performance of the successive IC scheme subject to the delay constraint, which may be imposed typically on most of service applications with a real-time transmission requirement, including speech and video applications. Our analysis demonstrates that the performance may be significantly improved by the groupwise successive interference cancellation (GSIC) scheme, which can be properly optimized to meet the given delay constraint.

• The Journal of Korean Institute of Communications and Information Sciences
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• v.29 no.9C
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• pp.1219-1226
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• 2004

The objective of this paper is to proposed a new Hybrid Interference Cancellation(HlC) receiver to cancel MAI in a multirate DS-CDMA system based on multiple processing gain(MPG). We propose a new improved HIC scheme that divides the active users with different data rates split into a number of groups for effectives cancellation Between each group, GW-PIC is performed to cancel other group signals and within them, SIC is carried out to remove multiple access interference in group. We analyze the performance of the proposed receiver in terms of the bit error rate(BER) and examine its performance. As a conclusion, computer simulations show that the proposed schemes outperforms adaptive multistage PIC and conventional SIC receiver over AWGN channel.

• Journal of the Institute of Electronics Engineers of Korea SD
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• v.39 no.6
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• pp.51-58
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• 2002

In this paper, a 155/311 Mb/s MUX/DEMUX chip using ECL macrocell away has been developed with a single device. This device for a 2.5 Gb/s SDH based transmission system is to interleave the parallel data of 51 Mb/s into 155 Mb/s(or 311 Mb/s) serial data output, and is to interleave a serial input bit stream of 155 Mb/s(or 311 Mb/s) into the parallel output of 51 Mb/s. The input and output of the device ate TTL compatible at the low-speed end, but 100k ECL compatible at the high-speed end. The device has been fabricated with Motorola ETL3200 macrocell away The fabricated chip shows the typical phase margin of 180 degrees and output data skew less than 220ps at the high-speed end.

• Proceedings of the Korean Institute of Navigation and Port Research Conference
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• 2009.06a
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• pp.467-470
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• 2009

A novel 8 V DC power source with an external series-parallel connection of 50 Dye-Sensitized Solar Cells(DSSCs) has been proposed. One DSC has the optimized length to width ratio of $5.2{\times}2.6$ cm and an active area 8 $cm^2$($4.62{\times}1.73$ cm) which attained a conversion efficiency of 4.2%. From the electrochemical impedance spectroscopic analysis, it was found that the resistance elements related to the Pt electrode and electrolyte interface behave like that of diode and the series resistance corresponds to the sum of the other resistance elements. In addition, the TEMoo mode pulsed Nd:YAG laser beam is used to improve the incident photon to current efficiency(IPCE) of DSSC. From this result, this novel 8V-0.38A DC power source shows stable performance with an energy conversion efficiency of about 4.5% under 1 sun illumination(AM 1.5, Pin of 100 $mW/cm^2$).

• The Transactions of the Korean Institute of Power Electronics
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• v.3 no.4
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• pp.353-364
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• 1998

This paper presents a systematic approach to the modeling of power electronic circuits with systemlongrightarrowlevel simulation l languages. It is shown that a circuit model reduces to one of four basic types according to input/output conditions. The e elementary models for single series components and shunt components are derived which are integrated to develop a m model of given converter circuit. The constraints imposed on the model development-matching input/output conditions a and avoiding algebraic loop-are discussed in relation to the realization example of a buck converter circuit model. It is s shown that the constraints can always be fullfilled by introducing fictitious interface blocks, which is generalized to the c concept of model transformation.