• Journal of Satellite, Information and Communications
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• v.1 no.2
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• pp.95-100
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• 2006

The COMS(Communication, Ocean and Meteorological Satellite) EPS(Electrical Power Subsystem) is derived from an enhanced Eurostar 3000 version. Eurostar 3000 EpS is fully autonomous operation in nominal conditions or in the event of a failure and provides a high level of reconfigure capability. This paper introduces the COMS EPS preliminary design result. COMS EPS consists of a battery, a solar arrat wing, a PSR(Power Supply Regulator), a PRU(Pyrotechnic Unit), a SDAM(Solar Array Drive Mechanism) and relay and fuse brackets. COMS EPS can offer a bus power capability of 3 kW. The solar array is made of a deployable wing with two panels. One type fo solar cells is selected ad GaAs/Ge triple junction cells. Li-ion battery is base lined with ten series cell module of five cells in parallel. PSR associated to battery and solar array wing generates a power bus fully regulated at 50 V. Power bus os centralized protection and distribution by relay and fuse brackets. PRU provides power for firing actuarors devices. The solar array wing is rotated by the SADM under control of the attitude orbit control subsystem. The control and monitoring of the EPS, especially of the battery, is performed by the PSR in combination with the on-board software.

• KEPCO Journal on Electric Power and Energy
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• v.2 no.4
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• pp.609-613
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• 2016

A hybrid charging method with serial and parallel architecture has been developed to resolve the unbalanced charge problem among battery cells for Electric Vehicles. In this method, the major charging is performed with serial part and the balancing is carried out with the parallel part, where the serial part is big and heavy but the parallel part is smaller and lighter than serial part. A sensor array to detect the individual battery cell voltage, duty rate control incorporated IGBTs, and battery management system are employed as the core parts of the proposed system.

• Journal of the Institute of Electronics Engineers of Korea SD
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• v.37 no.2
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• pp.78-84
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• 2000

The Viterbi decoders can be classified into serial Viterbi decoders and parallel Viterbi decoders. Parallel Viterbi decoders can handle higher data rates than serial Viterbl decoders. This paper designs and implements a fully parallel Viterbi decoder for high speed multimedia communications. For high speed operations, the ACS (Add-Compare-Select) module consisting of 64 PEs (Processing Elements) can compute one stage in a clock. In addition, the systolic away structure with 32 pipeline stages is developed for the TB (traceback) module. The implemented Viterbi decoder can support code rates 1/2, 2/3, 3/4, 5/6 and 7/8 using punctured codes. We have developed Verilog HDL models and performed logic synthesis. The 0.6 ${\mu}{\textrm}{m}$ SAMSUNG KG75000 SOG cell library has been used. The implemented Viterbi decoder has about 100,400 gates, and is running at 70 MHz in the worst case simulation.

• Transactions of the Korean Society of Mechanical Engineers A
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• v.33 no.5
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• pp.469-473
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• 2009

We present high-voltage liquid-electrolyte microbatteries, inspired from the high-voltage generation mechanism of electric eels using serially connected multiple-cell arrays. In the microbatteries, we purge air into the electrolyte filled in a channel layer to isolate serially connected multiple cell arrays using three surface-tension valves (cell-front, outlet, and cell-end valves). Compared to the previous multi-cell stack or interconnection, present microbatteries provide a reduced multi-cell charging time. We have designed and characterized four different prototypes C1, C10, C20, and C40 having 1, 10, 20, and 40 cells, respectively. In the experimental study, the threshold pressures of cell-front, outlet, and cell-end valves were measured as $460{\pm}47$, $1,000{\pm}53$, and $2,800{\pm}170$ Pa, respectively. The average charging time for C40 was measured as $26.8{\pm}4.9$ seconds where the electrolyte and air flow-rates are 100 and $10{\mu}l/min$, respectively. Microbatteries showed the maximum voltage of 12 V (C40), the maximum power density of $110{\mu}W/cm^2$ (C40), and the maximum power capacity of $2.1{\mu}Ah/cm^2$ (C40). We also proposed a tapered-channel to remove the reaction gas from the cell chamber using a surface tension effect. The present microbatteries are applicable to high-voltage portable power devices.

• Journal of the Institute of Electronics Engineers of Korea SC
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• v.37 no.1
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• pp.40-48
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• 2000

1A novel bipolar linear transconductor and its application to operational transconductance amplifier(OTA) for low-voltage low-power signal processing is proposed. The transconductor consists of a npn differential-pair with emitter degeneration resistor and a pnp differential-pair connected to the npn differential-pair in cascade. The bias current of the pnp differential-pair is used with the output current of the npn differential-pair for wide linearity and temperature stability. The OTA consists of the linear transconductor and a translinear current cell followed by three current mirrors. The proposed transconductor has superior linearity and low-voltage low-power characteristics when compared with the conventional transconductor. The experimental results show that the transconductor with transconductance of 50 ${\mu}S$ has a linearity error of less than ${\pm}$0.06% over an input voltage range from -2V to +2V at supply voltage ${\pm}$3V. Power dissipation of the transconductor was 2.44 mW. A prototype OTA with a transconductance of 25 ${\mu}S$ has been built with bipolar transistor array. The linearity of the OTA was same as the proposed transconductor. The OTA circuit also exhibits a transconductance that is linearly dependent on a bias current varying over four decades with a sensitivity of 0.5 S/A.

• Journal of the Korea Institute of Information Security & Cryptology
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• v.10 no.4
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• pp.81-93
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• 2000

In a methodological approach to improve the processing performance of modulo exponentiation which is the primary arithmetic in RSA crypto algorithm, we present a new RSA hardware architecture based on high-radix modulo multiplication and CRT(Chinese Remainder Theorem). By implementing the modulo multiplier using radix-16 arithmetic, we reduced the number of PE(Processing Element)s by quarter comparing to the binary arithmetic scheme. This leads to having the number of clock cycles and the delay of pipelining flip-flops be reduced by quarter respectively. Because the receiver knows p and q, factors of N, it is possible to apply the CRT to the decryption process. To use CRT, we made two s/2-bit multipliers operating in parallel at decryption, which accomplished 4 times faster performance than when not using the CRT. In encryption phase, the two s/2-bit multipliers can be connected to make a s-bit linear multiplier for the s-bit arithmetic operation. We limited the encryption exponent size up to 17-bit to maintain high speed, We implemented a linear array modulo multiplier by projecting horizontally the DG of Montgomery algorithm. The H/W proposed here performs encryption with 15Mbps bit-rate and decryption with 1.22Mbps, when estimated with reference to Samsung 0.5um CMOS Standard Cell Library, which is the fastest among the publications at present.